From 2bfc4f6dd443df68b40de5c694c31c9eb3e4e3dc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 Jun 2020 14:44:07 -0700 Subject: [PATCH] More fixes for RC bump --- generators/boom | 2 +- .../src/main/scala/config/TracegenConfigs.scala | 10 +++++----- generators/testchipip | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/generators/boom b/generators/boom index 0b60c278..96ac46f6 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 0b60c27879f8aa309537d5a535ea2c42e3dabefe +Subproject commit 96ac46f60261a98f1f1fa62fbd6a2fe9df5ba4bb diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index ec834f9f..e8aeeb29 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -9,7 +9,7 @@ class TraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -17,7 +17,7 @@ class NonBlockingTraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -26,7 +26,7 @@ class BoomTraceGenConfig extends Config( new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenL2Config extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -35,7 +35,7 @@ class NonBlockingTraceGenL2Config extends Config( new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenL2RingConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -45,4 +45,4 @@ class NonBlockingTraceGenL2RingConfig extends Config( new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) diff --git a/generators/testchipip b/generators/testchipip index 26891fac..29eb87c9 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 26891fac1d40c31348b6e6f16d730de705707094 +Subproject commit 29eb87c938a2106249b85e3b3dffd00046f5077c