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Remove firrtl_interpreter tests

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This commit is contained in:
Jerry Zhao
2023-07-12 13:57:31 -07:00
parent 29a2d91735
commit 27f4b83033
1 changed files with 98 additions and 98 deletions
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196
src/test/scala/barstools/macros/Functional.scala
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@@ -1,120 +1,120 @@
package barstools.macros package barstools.macros
import firrtl.ir.Circuit // import firrtl.ir.Circuit
import firrtl_interpreter.InterpretiveTester // import firrtl_interpreter.InterpretiveTester
// Functional tests on memory compiler outputs. // // Functional tests on memory compiler outputs.
// Synchronous write and read back. // // Synchronous write and read back.
class SynchronousReadAndWrite extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { // class SynchronousReadAndWrite extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 12 // override lazy val width = 12
override lazy val memDepth = BigInt(2048) // override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024) // override lazy val libDepth = BigInt(1024)
compile(mem, lib, v, synflops = true) // compile(mem, lib, v, synflops = true)
val result: Circuit = execute(mem, lib, synflops = true) // val result: Circuit = execute(mem, lib, synflops = true)
it should "run with InterpretedTester" in { // it should "run with InterpretedTester" in {
pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published // pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published
val addr1 = 0 // val addr1 = 0
val addr1val = 0xff // val addr1val = 0xff
val addr2 = 42 // val addr2 = 42
val addr2val = 0xf0 // val addr2val = 0xf0
val addr3 = 1 << 10 // val addr3 = 1 << 10
val addr3val = 1 << 10 // val addr3val = 1 << 10
val tester = new InterpretiveTester(result.serialize) // val tester = new InterpretiveTester(result.serialize)
//~ tester.setVerbose() // //~ tester.setVerbose()
tester.poke("outer_write_en", 0) // tester.poke("outer_write_en", 0)
tester.step() // tester.step()
// Write addresses and read them. // // Write addresses and read them.
tester.poke("outer_addr", addr1) // tester.poke("outer_addr", addr1)
tester.poke("outer_din", addr1val) // tester.poke("outer_din", addr1val)
tester.poke("outer_write_en", 1) // tester.poke("outer_write_en", 1)
tester.step() // tester.step()
tester.poke("outer_write_en", 0) // tester.poke("outer_write_en", 0)
tester.step() // tester.step()
tester.poke("outer_addr", addr2) // tester.poke("outer_addr", addr2)
tester.poke("outer_din", addr2val) // tester.poke("outer_din", addr2val)
tester.poke("outer_write_en", 1) // tester.poke("outer_write_en", 1)
tester.step() // tester.step()
tester.poke("outer_write_en", 0) // tester.poke("outer_write_en", 0)
tester.step() // tester.step()
tester.poke("outer_addr", addr3) // tester.poke("outer_addr", addr3)
tester.poke("outer_din", addr3val) // tester.poke("outer_din", addr3val)
tester.poke("outer_write_en", 1) // tester.poke("outer_write_en", 1)
tester.step() // tester.step()
tester.poke("outer_write_en", 0) // tester.poke("outer_write_en", 0)
tester.step() // tester.step()
tester.poke("outer_addr", addr1) // tester.poke("outer_addr", addr1)
tester.step() // tester.step()
tester.expect("outer_dout", addr1val) // tester.expect("outer_dout", addr1val)
tester.poke("outer_addr", addr2) // tester.poke("outer_addr", addr2)
tester.step() // tester.step()
tester.expect("outer_dout", addr2val) // tester.expect("outer_dout", addr2val)
tester.poke("outer_addr", addr3) // tester.poke("outer_addr", addr3)
tester.step() // tester.step()
tester.expect("outer_dout", addr3val) // tester.expect("outer_dout", addr3val)
} // }
} // }
// Test to verify that the circuit doesn't read combinationally based on addr // // Test to verify that the circuit doesn't read combinationally based on addr
// between two submemories. // // between two submemories.
class DontReadCombinationally extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator { // class DontReadCombinationally extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8 // override lazy val width = 8
override lazy val memDepth = BigInt(2048) // override lazy val memDepth = BigInt(2048)
override lazy val libDepth = BigInt(1024) // override lazy val libDepth = BigInt(1024)
compile(mem, lib, v, synflops = true) // compile(mem, lib, v, synflops = true)
val result: Circuit = execute(mem, lib, synflops = true) // val result: Circuit = execute(mem, lib, synflops = true)
it should "run with InterpretedTester" in { // it should "run with InterpretedTester" in {
pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published // pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published
val addr1 = 0 // val addr1 = 0
val addr1a = 1 // val addr1a = 1
val addr2 = 1 << 10 // val addr2 = 1 << 10
val tester = new InterpretiveTester(result.serialize) // val tester = new InterpretiveTester(result.serialize)
//~ tester.setVerbose() // //~ tester.setVerbose()
tester.poke("outer_write_en", 0) // tester.poke("outer_write_en", 0)
tester.step() // tester.step()
// Write two addresses, one in the lower submemory and the other in the // // Write two addresses, one in the lower submemory and the other in the
// higher submemory. // // higher submemory.
tester.poke("outer_addr", addr1) // tester.poke("outer_addr", addr1)
tester.poke("outer_din", 0x11) // tester.poke("outer_din", 0x11)
tester.poke("outer_write_en", 1) // tester.poke("outer_write_en", 1)
tester.step() // tester.step()
tester.poke("outer_addr", addr1a) // tester.poke("outer_addr", addr1a)
tester.poke("outer_din", 0x1a) // tester.poke("outer_din", 0x1a)
tester.poke("outer_write_en", 1) // tester.poke("outer_write_en", 1)
tester.step() // tester.step()
tester.poke("outer_addr", addr2) // tester.poke("outer_addr", addr2)
tester.poke("outer_din", 0xaa) // tester.poke("outer_din", 0xaa)
tester.poke("outer_write_en", 1) // tester.poke("outer_write_en", 1)
tester.step() // tester.step()
tester.poke("outer_write_en", 0) // tester.poke("outer_write_en", 0)
tester.poke("outer_addr", addr1) // tester.poke("outer_addr", addr1)
tester.step() // tester.step()
// Test that there is no combinational read. // // Test that there is no combinational read.
tester.poke("outer_addr", addr1) // tester.poke("outer_addr", addr1)
tester.expect("outer_dout", 0x11) // tester.expect("outer_dout", 0x11)
tester.poke("outer_addr", addr1a) // tester.poke("outer_addr", addr1a)
tester.expect("outer_dout", 0x11) // tester.expect("outer_dout", 0x11)
tester.poke("outer_addr", addr2) // tester.poke("outer_addr", addr2)
tester.expect("outer_dout", 0x11) // tester.expect("outer_dout", 0x11)
// And upon step it should work again. // // And upon step it should work again.
tester.step() // tester.step()
tester.expect("outer_addr", 0xaa) // tester.expect("outer_addr", 0xaa)
} // }
} // }