Remove firrtl_interpreter tests
This commit is contained in:
Jerry Zhao
@@ -1,120 +1,120 @@
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package barstools.macros
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import firrtl.ir.Circuit
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import firrtl_interpreter.InterpretiveTester
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// import firrtl.ir.Circuit
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// import firrtl_interpreter.InterpretiveTester
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// Functional tests on memory compiler outputs.
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// // Functional tests on memory compiler outputs.
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// Synchronous write and read back.
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class SynchronousReadAndWrite extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
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override lazy val width = 12
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override lazy val memDepth = BigInt(2048)
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override lazy val libDepth = BigInt(1024)
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// // Synchronous write and read back.
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// class SynchronousReadAndWrite extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
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// override lazy val width = 12
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// override lazy val memDepth = BigInt(2048)
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// override lazy val libDepth = BigInt(1024)
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compile(mem, lib, v, synflops = true)
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val result: Circuit = execute(mem, lib, synflops = true)
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// compile(mem, lib, v, synflops = true)
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// val result: Circuit = execute(mem, lib, synflops = true)
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it should "run with InterpretedTester" in {
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pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published
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// it should "run with InterpretedTester" in {
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// pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published
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val addr1 = 0
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val addr1val = 0xff
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val addr2 = 42
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val addr2val = 0xf0
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val addr3 = 1 << 10
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val addr3val = 1 << 10
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// val addr1 = 0
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// val addr1val = 0xff
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// val addr2 = 42
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// val addr2val = 0xf0
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// val addr3 = 1 << 10
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// val addr3val = 1 << 10
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val tester = new InterpretiveTester(result.serialize)
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//~ tester.setVerbose()
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// val tester = new InterpretiveTester(result.serialize)
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// //~ tester.setVerbose()
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tester.poke("outer_write_en", 0)
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tester.step()
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// tester.poke("outer_write_en", 0)
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// tester.step()
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// Write addresses and read them.
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tester.poke("outer_addr", addr1)
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tester.poke("outer_din", addr1val)
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tester.poke("outer_write_en", 1)
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tester.step()
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tester.poke("outer_write_en", 0)
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tester.step()
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tester.poke("outer_addr", addr2)
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tester.poke("outer_din", addr2val)
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tester.poke("outer_write_en", 1)
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tester.step()
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tester.poke("outer_write_en", 0)
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tester.step()
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tester.poke("outer_addr", addr3)
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tester.poke("outer_din", addr3val)
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tester.poke("outer_write_en", 1)
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tester.step()
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tester.poke("outer_write_en", 0)
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tester.step()
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// // Write addresses and read them.
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// tester.poke("outer_addr", addr1)
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// tester.poke("outer_din", addr1val)
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// tester.poke("outer_write_en", 1)
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// tester.step()
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// tester.poke("outer_write_en", 0)
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// tester.step()
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// tester.poke("outer_addr", addr2)
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// tester.poke("outer_din", addr2val)
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// tester.poke("outer_write_en", 1)
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// tester.step()
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// tester.poke("outer_write_en", 0)
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// tester.step()
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// tester.poke("outer_addr", addr3)
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// tester.poke("outer_din", addr3val)
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// tester.poke("outer_write_en", 1)
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// tester.step()
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// tester.poke("outer_write_en", 0)
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// tester.step()
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tester.poke("outer_addr", addr1)
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tester.step()
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tester.expect("outer_dout", addr1val)
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// tester.poke("outer_addr", addr1)
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// tester.step()
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// tester.expect("outer_dout", addr1val)
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tester.poke("outer_addr", addr2)
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tester.step()
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tester.expect("outer_dout", addr2val)
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// tester.poke("outer_addr", addr2)
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// tester.step()
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// tester.expect("outer_dout", addr2val)
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tester.poke("outer_addr", addr3)
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tester.step()
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tester.expect("outer_dout", addr3val)
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}
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}
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// tester.poke("outer_addr", addr3)
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// tester.step()
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// tester.expect("outer_dout", addr3val)
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// }
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// }
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// Test to verify that the circuit doesn't read combinationally based on addr
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// between two submemories.
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class DontReadCombinationally extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
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override lazy val width = 8
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override lazy val memDepth = BigInt(2048)
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override lazy val libDepth = BigInt(1024)
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// // Test to verify that the circuit doesn't read combinationally based on addr
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// // between two submemories.
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// class DontReadCombinationally extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
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// override lazy val width = 8
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// override lazy val memDepth = BigInt(2048)
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// override lazy val libDepth = BigInt(1024)
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compile(mem, lib, v, synflops = true)
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val result: Circuit = execute(mem, lib, synflops = true)
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// compile(mem, lib, v, synflops = true)
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// val result: Circuit = execute(mem, lib, synflops = true)
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it should "run with InterpretedTester" in {
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pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published
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// it should "run with InterpretedTester" in {
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// pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published
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val addr1 = 0
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val addr1a = 1
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val addr2 = 1 << 10
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// val addr1 = 0
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// val addr1a = 1
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// val addr2 = 1 << 10
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val tester = new InterpretiveTester(result.serialize)
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//~ tester.setVerbose()
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// val tester = new InterpretiveTester(result.serialize)
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// //~ tester.setVerbose()
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tester.poke("outer_write_en", 0)
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tester.step()
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// tester.poke("outer_write_en", 0)
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// tester.step()
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// Write two addresses, one in the lower submemory and the other in the
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// higher submemory.
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tester.poke("outer_addr", addr1)
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tester.poke("outer_din", 0x11)
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tester.poke("outer_write_en", 1)
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tester.step()
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tester.poke("outer_addr", addr1a)
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tester.poke("outer_din", 0x1a)
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tester.poke("outer_write_en", 1)
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tester.step()
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tester.poke("outer_addr", addr2)
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tester.poke("outer_din", 0xaa)
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tester.poke("outer_write_en", 1)
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tester.step()
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tester.poke("outer_write_en", 0)
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tester.poke("outer_addr", addr1)
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tester.step()
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// // Write two addresses, one in the lower submemory and the other in the
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// // higher submemory.
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// tester.poke("outer_addr", addr1)
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// tester.poke("outer_din", 0x11)
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// tester.poke("outer_write_en", 1)
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// tester.step()
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// tester.poke("outer_addr", addr1a)
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// tester.poke("outer_din", 0x1a)
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// tester.poke("outer_write_en", 1)
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// tester.step()
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// tester.poke("outer_addr", addr2)
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// tester.poke("outer_din", 0xaa)
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// tester.poke("outer_write_en", 1)
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// tester.step()
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// tester.poke("outer_write_en", 0)
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// tester.poke("outer_addr", addr1)
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// tester.step()
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// Test that there is no combinational read.
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tester.poke("outer_addr", addr1)
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tester.expect("outer_dout", 0x11)
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tester.poke("outer_addr", addr1a)
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tester.expect("outer_dout", 0x11)
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tester.poke("outer_addr", addr2)
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tester.expect("outer_dout", 0x11)
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// // Test that there is no combinational read.
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// tester.poke("outer_addr", addr1)
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// tester.expect("outer_dout", 0x11)
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// tester.poke("outer_addr", addr1a)
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// tester.expect("outer_dout", 0x11)
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// tester.poke("outer_addr", addr2)
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// tester.expect("outer_dout", 0x11)
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// And upon step it should work again.
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tester.step()
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tester.expect("outer_addr", 0xaa)
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}
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}
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// // And upon step it should work again.
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// tester.step()
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// tester.expect("outer_addr", 0xaa)
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// }
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// }
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