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This commit is contained in:
Edward Wang
2017-07-27 20:16:19 -07:00
committed by edwardcwang
parent e02f885e4b
commit 2126835df2
1 changed files with 2 additions and 2 deletions
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4
macros/src/test/scala/MacroCompilerSpec.scala
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@@ -204,8 +204,8 @@ trait HasSimpleTestGenerator {
val lib_name = "awesome_lib_mem" val lib_name = "awesome_lib_mem"
val lib_addr_width = ceilLog2(libDepth) val lib_addr_width = ceilLog2(libDepth)
// These generate "simple" SRAMs (1 masked read-write port) but can be // These generate "simple" SRAMs (1 masked read-write port) by default,
// overridden if need be. // but can be overridden if need be.
def generateLibSRAM() = generateSRAM(lib_name, "lib", libWidth, libDepth, libMaskGran, extraPorts) def generateLibSRAM() = generateSRAM(lib_name, "lib", libWidth, libDepth, libMaskGran, extraPorts)
def generateMemSRAM() = generateSRAM(mem_name, "outer", memWidth, memDepth, memMaskGran) def generateMemSRAM() = generateSRAM(mem_name, "outer", memWidth, memDepth, memMaskGran)