From 2126835df2fe64f585b5fb8acf8ffdf53396683a Mon Sep 17 00:00:00 2001 From: Edward Wang Date: Thu, 27 Jul 2017 20:16:19 -0700 Subject: [PATCH] Clarify comments --- macros/src/test/scala/MacroCompilerSpec.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/macros/src/test/scala/MacroCompilerSpec.scala b/macros/src/test/scala/MacroCompilerSpec.scala index e7133b9f..e1316608 100644 --- a/macros/src/test/scala/MacroCompilerSpec.scala +++ b/macros/src/test/scala/MacroCompilerSpec.scala @@ -204,8 +204,8 @@ trait HasSimpleTestGenerator { val lib_name = "awesome_lib_mem" val lib_addr_width = ceilLog2(libDepth) - // These generate "simple" SRAMs (1 masked read-write port) but can be - // overridden if need be. + // These generate "simple" SRAMs (1 masked read-write port) by default, + // but can be overridden if need be. def generateLibSRAM() = generateSRAM(lib_name, "lib", libWidth, libDepth, libMaskGran, extraPorts) def generateMemSRAM() = generateSRAM(mem_name, "outer", memWidth, memDepth, memMaskGran)