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changing clock name from clock_clock to clock_uncore_clock

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This commit is contained in:
Nayiri K
2023-06-23 13:13:56 -07:00
parent dde635245b
commit 20d6bf059f
5 changed files with 5 additions and 5 deletions
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2
vlsi/example-asap7.yml
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@@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals # Specify clock signals
vlsi.inputs.clocks: [ vlsi.inputs.clocks: [
{name: "clock_clock", period: "1ns", uncertainty: "0.1ns"} {name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"}
] ]
# Generate Make include to aid in flow # Generate Make include to aid in flow

2
vlsi/example-design.yml
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@@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals # Specify clock signals
vlsi.inputs.clocks: [ vlsi.inputs.clocks: [
{name: "clock_clock", period: "2ns", uncertainty: "0.1ns"} {name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"}
] ]
# Specify pin properties # Specify pin properties

2
vlsi/example-designs/sky130-commercial.yml
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@@ -2,7 +2,7 @@
# Specify clock signals # Specify clock signals
vlsi.inputs.clocks: [ vlsi.inputs.clocks: [
{name: "clock_clock", period: "30ns", uncertainty: "2ns"} {name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"}
] ]
# Placement Constraints # Placement Constraints

2
vlsi/example-designs/sky130-openroad.yml
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@@ -3,7 +3,7 @@
# Specify clock signals # Specify clock signals
# Relax the clock period for OpenROAD to meet timing # Relax the clock period for OpenROAD to meet timing
vlsi.inputs.clocks: [ vlsi.inputs.clocks: [
{name: "clock_clock", period: "50ns", uncertainty: "2ns"} {name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"}
] ]
# Flow parameters that yield a routable design with reasonable timing # Flow parameters that yield a routable design with reasonable timing

2
vlsi/example-sky130.yml
View File

@@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals # Specify clock signals
vlsi.inputs.clocks: [ vlsi.inputs.clocks: [
{name: "clock_clock", period: "20ns", uncertainty: "1ns"} {name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"}
] ]
# Generate Make include to aid in flow # Generate Make include to aid in flow