From 20d6bf059fb4dfa19b53ae4f558b20fe93014765 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 23 Jun 2023 13:13:56 -0700 Subject: [PATCH] changing clock name from clock_clock to clock_uncore_clock --- vlsi/example-asap7.yml | 2 +- vlsi/example-design.yml | 2 +- vlsi/example-designs/sky130-commercial.yml | 2 +- vlsi/example-designs/sky130-openroad.yml | 2 +- vlsi/example-sky130.yml | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index dbcadab0..6fc819aa 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index ebc2d6a6..3f46a443 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "2ns", uncertainty: "0.1ns"} + {name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"} ] # Specify pin properties diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml index b2ecfb26..f396af09 100644 --- a/vlsi/example-designs/sky130-commercial.yml +++ b/vlsi/example-designs/sky130-commercial.yml @@ -2,7 +2,7 @@ # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "30ns", uncertainty: "2ns"} + {name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"} ] # Placement Constraints diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index b52266b4..669d2f92 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -3,7 +3,7 @@ # Specify clock signals # Relax the clock period for OpenROAD to meet timing vlsi.inputs.clocks: [ - {name: "clock_clock", period: "50ns", uncertainty: "2ns"} + {name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"} ] # Flow parameters that yield a routable design with reasonable timing diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 5481c4a8..1cd281f7 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "20ns", uncertainty: "1ns"} + {name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow