changing clock name from clock_clock to clock_uncore_clock
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@@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf"
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# Specify clock signals
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vlsi.inputs.clocks: [
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{name: "clock_clock", period: "20ns", uncertainty: "1ns"}
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{name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"}
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]
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# Generate Make include to aid in flow
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