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Allow the PLL to request the max freq

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Abraham Gonzalez
2021-03-11 03:30:14 +00:00
parent d204ccd9fc
commit 1ebc0f7a7e
1 changed files with 1 additions and 1 deletions
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generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
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@@ -51,7 +51,7 @@ object FrequencyUtils {
require(!requestedOutputs.contains(0.0)) require(!requestedOutputs.contains(0.0))
val requestedFreqs = requestedOutputs.map(_.freqMHz) val requestedFreqs = requestedOutputs.map(_.freqMHz)
val fastestFreq = requestedFreqs.max val fastestFreq = requestedFreqs.max
require(fastestFreq < maximumAllowableFreqMHz) require(fastestFreq <= maximumAllowableFreqMHz)
val candidateFreqs = val candidateFreqs =
Seq.tabulate(Math.ceil(maximumAllowableFreqMHz / fastestFreq).toInt)(i => (i + 1) * fastestFreq) Seq.tabulate(Math.ceil(maximumAllowableFreqMHz / fastestFreq).toInt)(i => (i + 1) * fastestFreq)