From 1ebc0f7a7e19bf3279eeabddaa42a73469537491 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 11 Mar 2021 03:30:14 +0000 Subject: [PATCH] Allow the PLL to request the max freq --- .../src/main/scala/clocking/DividerOnlyClockGenerator.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala index 589d99c6..1723b756 100644 --- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala +++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala @@ -51,7 +51,7 @@ object FrequencyUtils { require(!requestedOutputs.contains(0.0)) val requestedFreqs = requestedOutputs.map(_.freqMHz) val fastestFreq = requestedFreqs.max - require(fastestFreq < maximumAllowableFreqMHz) + require(fastestFreq <= maximumAllowableFreqMHz) val candidateFreqs = Seq.tabulate(Math.ceil(maximumAllowableFreqMHz / fastestFreq).toInt)(i => (i + 1) * fastestFreq)