Allow the PLL to request the max freq

2021-03-11 03:30:14 +00:00
parent d204ccd9fc
commit 1ebc0f7a7e
1 changed files with 1 additions and 1 deletions
--- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
+++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
@@ -51,7 +51,7 @@ object FrequencyUtils {
    require(!requestedOutputs.contains(0.0))
    val requestedFreqs = requestedOutputs.map(_.freqMHz)
    val fastestFreq = requestedFreqs.max
-    require(fastestFreq < maximumAllowableFreqMHz)
+    require(fastestFreq <= maximumAllowableFreqMHz)

    val candidateFreqs =
      Seq.tabulate(Math.ceil(maximumAllowableFreqMHz / fastestFreq).toInt)(i => (i + 1) * fastestFreq)