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Hang the periphery TLSerial off a OBUS

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This commit is contained in:
Jerry Zhao
2023-05-25 11:29:03 -07:00
parent 436a6cb538
commit 1d50fb3115
1 changed files with 10 additions and 3 deletions
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13
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -2,30 +2,37 @@ package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{MBUS}
// A simple config demonstrating how to set up a basic chip in Chipyard
class ChipLikeQuadRocketConfig extends Config(
class ChipLikeRocketConfig extends Config(
//==================================
// Set up TestHarness
//==================================
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness
// NOTE: This only simulates properly in VCS
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach SimDRAM to serial-tl port
//==================================
// Set up tiles
//==================================
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add rational crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // 1 RocketTile
//==================================
// Set up I/O
//==================================
new testchipip.WithSerialTLWidth(4) ++
new testchipip.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
//==================================
// Set up buses
//==================================
new testchipip.WithOffchipBusManager(MBUS) ++
new testchipip.WithOffchipBus ++
//==================================
// Set up clock./reset
//==================================