From 1d50fb31156db0cc989725b5c79747e78d68a598 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 25 May 2023 11:29:03 -0700 Subject: [PATCH] Hang the periphery TLSerial off a OBUS --- .../src/main/scala/config/ChipConfigs.scala | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 1d717eae..e7c8ce9b 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -2,30 +2,37 @@ package chipyard import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.subsystem.{MBUS} // A simple config demonstrating how to set up a basic chip in Chipyard -class ChipLikeQuadRocketConfig extends Config( +class ChipLikeRocketConfig extends Config( //================================== // Set up TestHarness //================================== new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness // NOTE: This only simulates properly in VCS + new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach SimDRAM to serial-tl port //================================== // Set up tiles //================================== new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add rational crossings between RocketTile and uncore - new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // 1 RocketTile //================================== // Set up I/O //================================== new testchipip.WithSerialTLWidth(4) ++ new testchipip.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol - new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel + //================================== + // Set up buses + //================================== + new testchipip.WithOffchipBusManager(MBUS) ++ + new testchipip.WithOffchipBus ++ + //================================== // Set up clock./reset //==================================