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Enlarge serial width | Bugfix loadmem disable | Add TracerV

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This commit is contained in:
Abraham Gonzalez
2021-03-03 02:43:38 +00:00
parent a3e22c78de
commit 1d287bede5
3 changed files with 12 additions and 3 deletions
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2
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -216,7 +216,7 @@ class LBWIFRocketConfig extends Config(
// DEBUG: To check if UART works (with everything default but serdes slow and ramp up to 1GHz) // DEBUG: To check if UART works (with everything default but serdes slow and ramp up to 1GHz)
class DebugOffchipConfig extends Config( class DebugOffchipConfig extends Config(
new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialTLWidth(64) ++
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // SerDes <-async-> mbus. Remember SerDes master tied to fbus new testchipip.WithAsynchronousSerialSlaveCrossing ++ // SerDes <-async-> mbus. Remember SerDes master tied to fbus
new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast
new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ // controls SerDes freq. new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ // controls SerDes freq.

3
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -109,7 +109,8 @@ class WithOffchipNetworkSerialAXIBridge extends OverrideHarnessBinder({
ports.map({ port => ports.map({ port =>
val offchipNetwork = SerialAdapter.connectOffChipNetwork(system.serdesser.get, port, th.harnessReset) val offchipNetwork = SerialAdapter.connectOffChipNetwork(system.serdesser.get, port, th.harnessReset)
SerialBridge(port.bits.clock, offchipNetwork.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) SerialBridge(port.bits.clock, offchipNetwork.module.io.tsi_ser, p(SerialTLKey).map(v => MainMemoryConsts.globalName))
p(SerialTLKey).map(v => require(v.isMemoryDevice))
// connect SimAxiMem // connect SimAxiMem
(offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (axi4, edge) => (offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (axi4, edge) =>

10
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -251,22 +251,30 @@ class WithOffchipAXINoClksSetup(pbusFreqMHz: BigInt = 3200) extends Config(
// OLD: pbus @ 3200MHz, HW baud @ 3686400L AKA 115200 * 32 // OLD: pbus @ 3200MHz, HW baud @ 3686400L AKA 115200 * 32
// OLD: Linux @ 115200, SBI @ 115200 // OLD: Linux @ 115200, SBI @ 115200
// scale down to 100MHz before multipling up // scale down to 100MHz before multipling up
new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++ //new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++
new chipyard.config.WithUART(BigInt(3686400L)) ++
// Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock) // Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock)
new chipyard.config.WithNoDebug new chipyard.config.WithNoDebug
) )
class WithTracerV extends Config(
new WithTracerVBridge ++
new chipyard.config.WithTraceIO)
class FireSimDebugOffchipConfig extends Config( class FireSimDebugOffchipConfig extends Config(
new WithTracerV ++
new WithOffchipAXINoClksSetup(3200) ++ new WithOffchipAXINoClksSetup(3200) ++
new chipyard.DebugOffchipConfig new chipyard.DebugOffchipConfig
) )
class FireSimDebugOffchip2Config extends Config( class FireSimDebugOffchip2Config extends Config(
new WithTracerV ++
new WithOffchipAXINoClksSetup(3200) ++ new WithOffchipAXINoClksSetup(3200) ++
new chipyard.DebugOffchip2Config new chipyard.DebugOffchip2Config
) )
class FireSimDebugOffchip3Config extends Config( class FireSimDebugOffchip3Config extends Config(
new WithTracerV ++
new WithOffchipAXINoClksSetup(4000) ++ new WithOffchipAXINoClksSetup(4000) ++
new chipyard.DebugOffchip3Config new chipyard.DebugOffchip3Config
) )