From 1d287bede5fc4012b1ce8120fd00ffab98d8348e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 3 Mar 2021 02:43:38 +0000 Subject: [PATCH] Enlarge serial width | Bugfix loadmem disable | Add TracerV --- .../chipyard/src/main/scala/config/RocketConfigs.scala | 2 +- generators/firechip/src/main/scala/BridgeBinders.scala | 3 ++- generators/firechip/src/main/scala/TargetConfigs.scala | 10 +++++++++- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 2e6eb40f..4d93f8e9 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -216,7 +216,7 @@ class LBWIFRocketConfig extends Config( // DEBUG: To check if UART works (with everything default but serdes slow and ramp up to 1GHz) class DebugOffchipConfig extends Config( - new testchipip.WithSerialTLWidth(32) ++ + new testchipip.WithSerialTLWidth(64) ++ new testchipip.WithAsynchronousSerialSlaveCrossing ++ // SerDes <-async-> mbus. Remember SerDes master tied to fbus new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ // controls SerDes freq. diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 34a18f85..6f74b770 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -109,7 +109,8 @@ class WithOffchipNetworkSerialAXIBridge extends OverrideHarnessBinder({ ports.map({ port => val offchipNetwork = SerialAdapter.connectOffChipNetwork(system.serdesser.get, port, th.harnessReset) - SerialBridge(port.bits.clock, offchipNetwork.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) + SerialBridge(port.bits.clock, offchipNetwork.module.io.tsi_ser, p(SerialTLKey).map(v => MainMemoryConsts.globalName)) + p(SerialTLKey).map(v => require(v.isMemoryDevice)) // connect SimAxiMem (offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (axi4, edge) => diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 619137fd..de9e9cf7 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -251,22 +251,30 @@ class WithOffchipAXINoClksSetup(pbusFreqMHz: BigInt = 3200) extends Config( // OLD: pbus @ 3200MHz, HW baud @ 3686400L AKA 115200 * 32 // OLD: Linux @ 115200, SBI @ 115200 // scale down to 100MHz before multipling up - new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++ + //new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++ + new chipyard.config.WithUART(BigInt(3686400L)) ++ // Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock) new chipyard.config.WithNoDebug ) +class WithTracerV extends Config( + new WithTracerVBridge ++ + new chipyard.config.WithTraceIO) + class FireSimDebugOffchipConfig extends Config( + new WithTracerV ++ new WithOffchipAXINoClksSetup(3200) ++ new chipyard.DebugOffchipConfig ) class FireSimDebugOffchip2Config extends Config( + new WithTracerV ++ new WithOffchipAXINoClksSetup(3200) ++ new chipyard.DebugOffchip2Config ) class FireSimDebugOffchip3Config extends Config( + new WithTracerV ++ new WithOffchipAXINoClksSetup(4000) ++ new chipyard.DebugOffchip3Config )