Enlarge serial width | Bugfix loadmem disable | Add TracerV
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@@ -109,7 +109,8 @@ class WithOffchipNetworkSerialAXIBridge extends OverrideHarnessBinder({
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ports.map({ port =>
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val offchipNetwork = SerialAdapter.connectOffChipNetwork(system.serdesser.get, port, th.harnessReset)
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SerialBridge(port.bits.clock, offchipNetwork.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
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SerialBridge(port.bits.clock, offchipNetwork.module.io.tsi_ser, p(SerialTLKey).map(v => MainMemoryConsts.globalName))
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p(SerialTLKey).map(v => require(v.isMemoryDevice))
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// connect SimAxiMem
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(offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (axi4, edge) =>
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