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Add debug Clock Tap IO

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This commit is contained in:
Jerry Zhao
2023-12-15 13:53:11 -08:00
parent d828879a7d
commit 1d05eda438
3 changed files with 20 additions and 4 deletions
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6
generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
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@@ -22,5 +22,11 @@ trait CanHaveClockTap { this: BaseSubsystem =>
val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap")))) val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
val clockTapDivider = LazyModule(new ClockDivider(tapParams.divider)) val clockTapDivider = LazyModule(new ClockDivider(tapParams.divider))
clockTap := clockTapDivider.node := locateTLBusWrapper(tapParams.busWhere).fixedClockNode clockTap := clockTapDivider.node := locateTLBusWrapper(tapParams.busWhere).fixedClockNode
clockTap
} }
val clockTapIO = clockTapNode.map { node => InModuleBody {
val clock_tap = IO(Output(Clock()))
clock_tap := node.in.head._1.clock
clock_tap
}}
} }

11
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
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@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey, ClockPort, ResetPort} import chipyard.iobinders._
import freechips.rocketchip.prci._ import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
@@ -119,3 +119,12 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
} }
} }
}) })
class WithClockTapIOCells extends OverrideIOBinder({
(system: CanHaveClockTap) => {
system.clockTapIO.map { tap =>
val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
(Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
}.getOrElse((Nil, Nil))
}
})

7
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -51,9 +51,10 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithUARTTSIPunchthrough ++ new chipyard.iobinders.WithUARTTSIPunchthrough ++
new chipyard.iobinders.WithNMITiedOff ++ new chipyard.iobinders.WithNMITiedOff ++
// By default, punch out IOs to the Harness new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio
new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks
Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus