From 1d05eda438f43371b153081a5279ea42365189a6 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Fri, 15 Dec 2023 13:53:11 -0800
Subject: [PATCH] Add debug Clock Tap IO

---
 .../src/main/scala/clocking/CanHaveClockTap.scala     |  6 ++++++
 .../src/main/scala/clocking/ClockBinders.scala        | 11 ++++++++++-
 .../src/main/scala/config/AbstractConfig.scala        |  7 ++++---
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
index 798dfda8..0bf7242b 100644
--- a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
+++ b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
@@ -22,5 +22,11 @@ trait CanHaveClockTap { this: BaseSubsystem =>
     val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
     val clockTapDivider = LazyModule(new ClockDivider(tapParams.divider))
     clockTap := clockTapDivider.node := locateTLBusWrapper(tapParams.busWhere).fixedClockNode
+    clockTap
   }
+  val clockTapIO = clockTapNode.map { node => InModuleBody {
+    val clock_tap = IO(Output(Clock()))
+    clock_tap := node.in.head._1.clock
+    clock_tap
+  }}
 }
diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
index 36d1fa2f..0a5c09e7 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey, ClockPort, ResetPort}
+import chipyard.iobinders._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.subsystem._
@@ -119,3 +119,12 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
     }
   }
 })
+
+class WithClockTapIOCells extends OverrideIOBinder({
+  (system: CanHaveClockTap) => {
+    system.clockTapIO.map { tap =>
+      val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
+      (Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
+    }.getOrElse((Nil, Nil))
+  }
+})
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index a08abb6d..43cfc110 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -51,9 +51,10 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithUARTTSIPunchthrough ++
   new chipyard.iobinders.WithNMITiedOff ++
 
-  // By default, punch out IOs to the Harness
-  new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
+  new chipyard.clocking.WithClockTapIOCells ++                      // Default generate a clock tapio
+  new chipyard.clocking.WithPassthroughClockGenerator ++            // Default punch out IOs to the Harness
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore",    // Default merge all the bus clocks
+    Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
   new chipyard.config.WithPeripheryBusFrequency(500.0) ++           // Default 500 MHz pbus
   new chipyard.config.WithMemoryBusFrequency(500.0) ++              // Default 500 MHz mbus