Update sodor package structure
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generators/chipyard/src/main/scala/config/SodorConfigs.scala
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generators/chipyard/src/main/scala/config/SodorConfigs.scala
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package chipyard
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import chisel3._
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import freechips.rocketchip.config.{Config}
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class SodorConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
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new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
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new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
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new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
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new testchipip.WithTSI ++ // use testchipip serial offchip link
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new chipyard.config.WithBootROM ++ // use default bootrom
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new chipyard.config.WithUART ++ // add a UART
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
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new sodor.common.WithNSodorCores(1) ++ // single Ariane core
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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Submodule generators/riscv-sodor updated: 607f346ff2...5e6a775ded
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