From 1933fd8cbe21d697fafeebebabe50c775e65c55a Mon Sep 17 00:00:00 2001
From: Zitao Fang <zitaofang@berkeley.edu>
Date: Tue, 14 Jul 2020 12:10:12 -0700
Subject: [PATCH] Update sodor package structure

---
 .../src/main/scala/config/SodorConfigs.scala  | 20 +++++++++++++++++++
 generators/riscv-sodor                        |  2 +-
 2 files changed, 21 insertions(+), 1 deletion(-)
 create mode 100644 generators/chipyard/src/main/scala/config/SodorConfigs.scala

diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
new file mode 100644
index 00000000..dfcfebe7
--- /dev/null
+++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -0,0 +1,20 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+class SodorConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
+  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
+  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithUART ++                                // add a UART
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new sodor.common.WithNSodorCores(1) ++                         // single Ariane core
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index 607f346f..5e6a775d 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit 607f346ff2e92977dcadda6cbd5b85589edcfbea
+Subproject commit 5e6a775ded0c19719f61acbae11874478bc9a8b5