made vlsi flow slightly cleaner

.github/workflows/chipyard-full-flow.yml

@@ -142,10 +142,6 @@ jobs:
           echo "drc.magic.magic_bin: $PWD/.conda-signoff/bin/magic" >> tutorial.yml
           echo "lvs.netgen.netgen_bin: $PWD/.conda-signoff/bin/netgen" >> tutorial.yml
           echo "" >> tutorial.yml
-          echo "# RocketTile clock name is 'clock'" >> tutorial.yml
-          echo "vlsi.inputs.clocks: [" >> tutorial.yml
-          echo "  {name: clock, period: 30ns, uncertainty: 3ns}" >> tutorial.yml
-          echo "]" >> tutorial.yml
           echo "# speed up tutorial runs & declutter log output" >> tutorial.yml
           echo "par.openroad.timing_driven: false" >> tutorial.yml
           echo "par.openroad.write_reports: false" >> tutorial.yml
@@ -154,9 +150,9 @@ jobs:
           conda config --remove channels defaults
 
           export tutorial=sky130-openroad
-          export EXTRA_CONFS="example-designs/sky130-openroad-rockettile.yml tutorial.yml"
+          export EXTRA_CONFS=tutorial.yml
           export VLSI_TOP=RocketTile
-          make buildfile
+          make buildfile -B
           make syn
           # openroad freezes during some write commands after detailed route
           # so need to stop the flow & run last step separately

conda-reqs/chipyard.yaml

@@ -101,6 +101,7 @@ dependencies:
 
     # hammer packages
     - sty
+    - open_pdks.sky130a
     - pip:
         - hammer-vlsi[asap7]==1.0.4
 
@@ -135,9 +136,6 @@ dependencies:
     - pip:
         - sure
         - pylddwrap
-    
-    # hammer sky130 open-source vlsi flow
-    - open_pdks.sky130a
 
     # firesim ci shared packages
     - boto3