Sync works to my laptop

This commit is contained in:
Zitao Fang
2020-05-25 10:47:58 -07:00
parent adb85c98ca
commit 15c1f5adba
2 changed files with 34 additions and 3 deletions

View File

@@ -23,6 +23,7 @@ import sifive.blocks.devices.spi._
import chipyard.{BuildTop, BuildSystem}
import chipyard.{CoreRegistrar, CoreRegisterEntryBase}
import chipyard.hlist
/**
* TODO: Why do we need this?
@@ -147,6 +148,12 @@ class WithControlCore extends Config((site, here, up) => {
case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
})
class WithTraceIOHMap extends ConfigHMap {
override def apply[I](v: I) = (site, here, up) => {
}
}
class WithTraceIO extends Config((site, here, up) => {
val coreMatch: List[CoreRegisterEntryBase] => PartialFunction[Any,Any] =
coreList => coreList match {