Sync works to my laptop
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@@ -23,6 +23,7 @@ import sifive.blocks.devices.spi._
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import chipyard.{BuildTop, BuildSystem}
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import chipyard.{CoreRegistrar, CoreRegisterEntryBase}
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import chipyard.hlist
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/**
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* TODO: Why do we need this?
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@@ -147,6 +148,12 @@ class WithControlCore extends Config((site, here, up) => {
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case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
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})
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class WithTraceIOHMap extends ConfigHMap {
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override def apply[I](v: I) = (site, here, up) => {
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}
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}
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class WithTraceIO extends Config((site, here, up) => {
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val coreMatch: List[CoreRegisterEntryBase] => PartialFunction[Any,Any] =
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coreList => coreList match {
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