From 15c1f5adba5d6c56748573beaa32432a437338d4 Mon Sep 17 00:00:00 2001
From: Zitao Fang <zitaofang@berkeley.edu>
Date: Mon, 25 May 2020 10:47:58 -0700
Subject: [PATCH] Sync works to my laptop

---
 .../src/main/scala/ConfigFragments.scala      |  7 +++++
 .../src/main/scala/CoreRegistrar.scala        | 30 +++++++++++++++++--
 2 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala
index 6eca517f..cdf84327 100644
--- a/generators/chipyard/src/main/scala/ConfigFragments.scala
+++ b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -23,6 +23,7 @@ import sifive.blocks.devices.spi._
 
 import chipyard.{BuildTop, BuildSystem}
 import chipyard.{CoreRegistrar, CoreRegisterEntryBase}
+import chipyard.hlist
 
 /**
  * TODO: Why do we need this?
@@ -147,6 +148,12 @@ class WithControlCore extends Config((site, here, up) => {
   case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
 })
 
+class WithTraceIOHMap extends ConfigHMap {
+  override def apply[I](v: I) = (site, here, up) => {
+    
+  }
+}
+
 class WithTraceIO extends Config((site, here, up) => {
   val coreMatch: List[CoreRegisterEntryBase] => PartialFunction[Any,Any] =
     coreList => coreList match {
diff --git a/generators/chipyard/src/main/scala/CoreRegistrar.scala b/generators/chipyard/src/main/scala/CoreRegistrar.scala
index b1503361..766172d1 100644
--- a/generators/chipyard/src/main/scala/CoreRegistrar.scala
+++ b/generators/chipyard/src/main/scala/CoreRegistrar.scala
@@ -1,5 +1,8 @@
 package chipyard
 
+import scala.reflect.ClassTag
+import scala.reflect.runtime.universe._
+
 import chisel3._
 
 import freechips.rocketchip.config.{Parameters, Config, Field, View}
@@ -16,16 +19,27 @@ sealed trait CoreRegisterEntryBase {
   type TileParams <: CoreParams
   def tilesKey: Field[Seq[TileParams]]
   def crossingKey: Field[Seq[RocketCrossingParams]]
+
+  def findTilesWithFilter(view: View, p: Any => View): PartialFunction[Any, Seq[AnyRef]]
+
   def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any]
   def instantiateTile(param: TileParams, crossing: RocketCrossingParams,
     logicalTreeNode: LogicalTreeNode, p: Parameters): Option[BaseTile]
 }
 
-class CoreRegisterEntry[TileParamsT <: CoreParams, TileT <: BaseTile](tk: Field[Seq[TileParamsT]], ck: Field[Seq[RocketCrossingParams]],
-  tileInstantiator: (TileParamsT, RocketCrossingParams, LookupByHartIdImpl, LogicalTreeNode, Parameters) => TileT) extends CoreRegisterEntryBase {
+class CoreRegisterEntry[TileParamsT <: CoreParams, TileT <: BaseTile](
+  tk: Field[Seq[TileParamsT]],
+  ck: Field[Seq[RocketCrossingParams]],
+  tileInstantiator: (TileParamsT, RocketCrossingParams, LookupByHartIdImpl, LogicalTreeNode, Parameters) => TileT
+) extends CoreRegisterEntryBase {
   type TileParams = TileParamsT
   def tilesKey = tk
   def crossingKey = ck
+
+  def findTilesWithFilter(view: View, p: Any => View) = {
+    case key if (key == tk && p(tk)) => view(tk)
+  }
+
   def enableTileTrace(site: View, here: View, up: View): PartialFunction[Any, Any] = {
     case in if in == tilesKey => up(this.tilesKey) map (tile => tile.copy(trace = true))
   }
@@ -41,4 +55,14 @@ object CoreRegistrar {
     // ADD YOUR CORE DEFINITION HERE
     new CoreRegisterEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey, ((a, b, c, d, p) => {new ArianeTile(a, b, c, d)}))
   )
-}
\ No newline at end of file
+}
+
+// Core Generic Config - change properties in the given map
+class GenericConfig(properties: Map[String, Any], filterFunc: Any => Bool = (_ => true)) {
+  val configFunc: (View, View, View) => PartialFunction[Any, Any] = ((site, here, up) => key => {
+    val tiles = CoreRegistrar.cores flatMap _.findTilesWithFilter(up, filterFunc).lift(key)
+    if (tiles.size == 0) None else Some(tiles map (tile => {
+      val method = ClassTag(tile.getClass).member(TermName(methodName)).asMethod
+    })).unlift
+  }).unlift
+}