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fix verilator build

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This commit is contained in:
Howard Mao
2017-06-22 17:41:48 -07:00
parent 9a9ebea207
commit 119e563ea6
4 changed files with 13 additions and 4 deletions
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5
src/main/scala/example/Configs.scala
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@@ -3,9 +3,12 @@ package example
import config.{Parameters, Config} import config.{Parameters, Config}
import testchipip.WithSerialAdapter import testchipip.WithSerialAdapter
import coreplex.WithRoccExample import coreplex.WithRoccExample
import rocketchip.WithoutTLMonitors
class DefaultExampleConfig extends Config( class DefaultExampleConfig extends Config(
new WithSerialAdapter ++ new rocketchip.DefaultConfig) new WithoutTLMonitors ++
new WithSerialAdapter ++
new rocketchip.DefaultConfig)
class RoccExampleConfig extends Config( class RoccExampleConfig extends Config(
new WithRoccExample ++ new DefaultExampleConfig) new WithRoccExample ++ new DefaultExampleConfig)

2
testchipip

Submodule testchipip updated: 82db791a5f...058e50a229

8
verisim/Makefile
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@@ -24,10 +24,15 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG)
sim_vsrcs = \ sim_vsrcs = \
$(build_dir)/$(long_name).v \ $(build_dir)/$(long_name).v \
$(base_dir)/testchipip/vsrc/SimSerial.v $(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
$(base_dir)/testchipip/vsrc/SimSerial.v \
$(base_dir)/testchipip/vsrc/SimBlockDevice.v
sim_csrcs = \ sim_csrcs = \
$(base_dir)/testchipip/csrc/SimSerial.cc \ $(base_dir)/testchipip/csrc/SimSerial.cc \
$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
$(base_dir)/testchipip/csrc/blkdev.cc \
$(base_dir)/testchipip/csrc/verilator-harness.cc $(base_dir)/testchipip/csrc/verilator-harness.cc
model_dir = $(build_dir)/$(long_name) model_dir = $(build_dir)/$(long_name)
@@ -40,6 +45,7 @@ model_mk = $(model_dir)/V$(MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(MODEL).mk model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
$(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR) $(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \ -o $(sim) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \

2
verisim/Makefrag-verilator
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@@ -31,5 +31,5 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
--output-split 20000 \ --output-split 20000 \
-Wno-STMTDLY --x-assign unique \ -Wno-STMTDLY --x-assign unique \
-I$(base_dir)/testchipip/vsrc \ -I$(base_dir)/testchipip/vsrc -I$(base_dir)/rocket-chip/vsrc \
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/rocket-chip/csrc/verilator.h" -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/rocket-chip/csrc/verilator.h"