diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala
index 8a0ea8bc..e1c48f8d 100644
--- a/src/main/scala/example/Configs.scala
+++ b/src/main/scala/example/Configs.scala
@@ -3,9 +3,12 @@ package example
 import config.{Parameters, Config}
 import testchipip.WithSerialAdapter
 import coreplex.WithRoccExample
+import rocketchip.WithoutTLMonitors
 
 class DefaultExampleConfig extends Config(
-  new WithSerialAdapter ++ new rocketchip.DefaultConfig)
+  new WithoutTLMonitors ++
+  new WithSerialAdapter ++
+  new rocketchip.DefaultConfig)
 
 class RoccExampleConfig extends Config(
   new WithRoccExample ++ new DefaultExampleConfig)
diff --git a/testchipip b/testchipip
index 82db791a..058e50a2 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 82db791a5fa923604dc622673fddfb6bade9d24e
+Subproject commit 058e50a2292a6e2e756a6f70f2afb6131d758c5c
diff --git a/verisim/Makefile b/verisim/Makefile
index 0379dc04..5ad1eb6b 100644
--- a/verisim/Makefile
+++ b/verisim/Makefile
@@ -24,10 +24,15 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG)
 
 sim_vsrcs = \
 	$(build_dir)/$(long_name).v \
-	$(base_dir)/testchipip/vsrc/SimSerial.v
+	$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
+	$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
+	$(base_dir)/testchipip/vsrc/SimSerial.v \
+	$(base_dir)/testchipip/vsrc/SimBlockDevice.v
 
 sim_csrcs = \
 	$(base_dir)/testchipip/csrc/SimSerial.cc \
+	$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
+	$(base_dir)/testchipip/csrc/blkdev.cc \
 	$(base_dir)/testchipip/csrc/verilator-harness.cc
 
 model_dir = $(build_dir)/$(long_name)
@@ -40,6 +45,7 @@ model_mk = $(model_dir)/V$(MODEL).mk
 model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
 
 $(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR)
+	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
 	-o $(sim) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
diff --git a/verisim/Makefrag-verilator b/verisim/Makefrag-verilator
index dd178191..54091517 100644
--- a/verisim/Makefrag-verilator
+++ b/verisim/Makefrag-verilator
@@ -31,5 +31,5 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
   +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
   --output-split 20000 \
 	-Wno-STMTDLY --x-assign unique \
-  -I$(base_dir)/testchipip/vsrc \
+  -I$(base_dir)/testchipip/vsrc -I$(base_dir)/rocket-chip/vsrc \
   -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/rocket-chip/csrc/verilator.h"