fix verilator build

2017-06-22 17:41:48 -07:00
parent 9a9ebea207
commit 119e563ea6
4 changed files with 13 additions and 4 deletions
--- a/verisim/Makefrag-verilator
+++ b/verisim/Makefrag-verilator
@@ -31,5 +31,5 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
  +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
  --output-split 20000 \
 	-Wno-STMTDLY --x-assign unique \
-  -I$(base_dir)/testchipip/vsrc \
+  -I$(base_dir)/testchipip/vsrc -I$(base_dir)/rocket-chip/vsrc \
  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/rocket-chip/csrc/verilator.h"