Update docs/Advanced-Concepts/Chip-Communication.rst

Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>

docs/Advanced-Concepts/Chip-Communication.rst

@@ -210,7 +210,7 @@ Bringup Setup of the Example Test Chip after Tapeout
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 Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link.
-For example, some Berkeley tapeouts of Chipyard chips have an FPGA running a RISC-V soft-core that is able to speak to the DUT.
+For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC).
 This RISC-V soft-core would serve as the host of the test that will run on the DUT.
 This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``SerialAdapter`` / ``TLSerdesser`` programmed on the FPGA.
 Once the commands are converted to serialized TileLink, then they can be sent over some medium to the DUT