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Rename testchip_fesvr to testchip_tsi

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This commit is contained in:
Jerry Zhao
2020-10-09 09:34:20 -07:00
parent 25129c27ca
commit 0c46ed1676
3 changed files with 4 additions and 4 deletions
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2
generators/testchipip

Submodule generators/testchipip updated: 9cf31acea5...56bfaa3f9b

4
generators/utilities/src/main/scala/Simulator.scala
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@@ -83,8 +83,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
} }
def resources(sim: Simulator): Seq[String] = Seq( def resources(sim: Simulator): Seq[String] = Seq(
"/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/SimSerial.cc",
"/testchipip/csrc/testchip_fesvr.cc", "/testchipip/csrc/testchip_tsi.cc",
"/testchipip/csrc/testchip_fesvr.h", "/testchipip/csrc/testchip_tsi.h",
"/testchipip/csrc/SimDRAM.cc", "/testchipip/csrc/SimDRAM.cc",
"/testchipip/csrc/mm.h", "/testchipip/csrc/mm.h",
"/testchipip/csrc/mm.cc", "/testchipip/csrc/mm.cc",

2
sims/firesim

Submodule sims/firesim updated: dd20a99f33...6318184f30