From 0c46ed167633ebe948ac746f9e0eccd9ab69b361 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Fri, 9 Oct 2020 09:34:20 -0700
Subject: [PATCH] Rename testchip_fesvr to testchip_tsi

---
 generators/testchipip                               | 2 +-
 generators/utilities/src/main/scala/Simulator.scala | 4 ++--
 sims/firesim                                        | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/generators/testchipip b/generators/testchipip
index 9cf31ace..56bfaa3f 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 9cf31acea528543896f04457573454a3e51f1e6a
+Subproject commit 56bfaa3f9bcd11206d93fdfa3c8e7656665e462a
diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala
index 02224fdb..f40ad032 100644
--- a/generators/utilities/src/main/scala/Simulator.scala
+++ b/generators/utilities/src/main/scala/Simulator.scala
@@ -83,8 +83,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
   }
   def resources(sim: Simulator): Seq[String] = Seq(
     "/testchipip/csrc/SimSerial.cc",
-    "/testchipip/csrc/testchip_fesvr.cc",
-    "/testchipip/csrc/testchip_fesvr.h",
+    "/testchipip/csrc/testchip_tsi.cc",
+    "/testchipip/csrc/testchip_tsi.h",
     "/testchipip/csrc/SimDRAM.cc",
     "/testchipip/csrc/mm.h",
     "/testchipip/csrc/mm.cc",
diff --git a/sims/firesim b/sims/firesim
index dd20a99f..6318184f 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit dd20a99f33eba31ffa2d6c7e9fc914445224d4e9
+Subproject commit 6318184f304315a94b5eb5c670f0eec1a3205f59