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Merge pull request #115 from ucb-bar/rebar-dev-rmv-sim-flags

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Remove CHISEL_ARGS
This commit is contained in:
Abraham Gonzalez
2019-06-03 20:09:05 -07:00
committed by GitHub
parent e44b78a0c1 51960f4345
commit 0994299cac
1 changed files with 1 additions and 3 deletions
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4
common.mk
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@@ -37,11 +37,9 @@ $(sim_dotf): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/
#########################################################################################
# create firrtl file rule and variables
#########################################################################################
CHISEL_ARGS ?=
$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(CHISEL_ARGS) $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"
cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"
#########################################################################################
# create verilog files rules and variables