Clean up code
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@@ -3,19 +3,17 @@ package chipyard.fpga.vcu118
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import chisel3._
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import chisel3.experimental.{IO}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
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import freechips.rocketchip.config.{Parameters}
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import freechips.rocketchip.tilelink.{TLClientNode}
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import sifive.fpgashells.shell.xilinx._
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import sifive.fpgashells.ip.xilinx._
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import sifive.fpgashells.shell._
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import sifive.fpgashells.clocks._
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import sifive.fpgashells.shell.xilinx.{VCU118ShellBasicOverlays, UARTVCU118ShellPlacer, SDIOVCU118ShellPlacer, JTAGDebugBScanVCU118ShellPlacer, JTAGDebugVCU118ShellPlacer, cJTAGDebugVCU118ShellPlacer, PCIeVCU118FMCShellPlacer, PCIeVCU118EdgeShellPlacer, VCU118ShellPMOD, ChipLinkVCU118PlacedOverlay}
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import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
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import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, ClockInputShellInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, SPIOverlayKey, SPIDesignInput, SPIShellInput, JTAGDebugOverlayKey, JTAGDebugShellInput, JTAGDebugBScanOverlayKey, JTAGDebugBScanShellInput, cJTAGDebugOverlayKey, cJTAGDebugShellInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput, DDRShellInput}
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import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
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import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
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import chipyard.{HasHarnessSignalReferences, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey}
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import chipyard.iobinders.{HasIOBinders}
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