From 0724431873663ab64cf719d1e8e280ef34905d2b Mon Sep 17 00:00:00 2001 From: Lori Li Date: Wed, 30 Nov 2022 16:56:09 +0900 Subject: [PATCH] Clean up code --- fpga/src/main/scala/arty/Configs.scala | 7 ++- fpga/src/main/scala/arty/HarnessBinders.scala | 58 +++++++++---------- fpga/src/main/scala/arty/IOBinders.scala | 3 +- fpga/src/main/scala/vc707/Configs.scala | 18 +++--- .../src/main/scala/vc707/HarnessBinders.scala | 2 +- fpga/src/main/scala/vc707/TestHarness.scala | 8 +-- fpga/src/main/scala/vcu118/Configs.scala | 6 +- fpga/src/main/scala/vcu118/TestHarness.scala | 20 +++---- 8 files changed, 59 insertions(+), 63 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 66391b41..1c81f481 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -26,6 +26,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => { debugIdleCycles = 5) case SerialTLKey => None // remove serialized tl port }) + // DOC include start: AbstractArty and Rocket class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ @@ -33,9 +34,11 @@ class WithArtyTweaks extends Config( new WithArtyResetHarnessBinder ++ new WithDebugResetPassthrough ++ new WithDefaultPeripherals ++ - new freechips.rocketchip.subsystem.WithNBreakpoints(2)) + new freechips.rocketchip.subsystem.WithNBreakpoints(2) +) class TinyRocketArtyConfig extends Config( new WithArtyTweaks ++ - new chipyard.TinyRocketConfig) + new chipyard.TinyRocketConfig +) // DOC include end: AbstractArty and Rocket diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index aaec1a86..4e90e858 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -2,13 +2,12 @@ package chipyard.fpga.arty import chisel3._ -import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} import freechips.rocketchip.jtag.{JTAGIO} -import freechips.rocketchip.subsystem._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pinctrl._ +import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp} +import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort} +import sifive.blocks.devices.pinctrl.{BasePin} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} @@ -32,39 +31,38 @@ class WithArtyResetHarnessBinder extends ComposeHarnessBinder({ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => { ports.map { - case j: JTAGChipIO => - withClockAndReset(th.buildtopClock, th.hReset) { - val jtag_wire = Wire(new JTAGIO) - jtag_wire.TDO.data := j.TDO - jtag_wire.TDO.driven := true.B - j.TCK := jtag_wire.TCK - j.TMS := jtag_wire.TMS - j.TDI := jtag_wire.TDI + case j: JTAGChipIO => withClockAndReset(th.buildtopClock, th.hReset) { + val jtag_wire = Wire(new JTAGIO) + jtag_wire.TDO.data := j.TDO + jtag_wire.TDO.driven := true.B + j.TCK := jtag_wire.TCK + j.TMS := jtag_wire.TMS + j.TDI := jtag_wire.TDI - val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag") + val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag") - JTAGPinsFromPort(io_jtag, jtag_wire) + JTAGPinsFromPort(io_jtag, jtag_wire) - io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool + io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool - IOBUF(th.jd_5, io_jtag.TMS) - PULLUP(th.jd_5) + IOBUF(th.jd_5, io_jtag.TMS) + PULLUP(th.jd_5) - IOBUF(th.jd_4, io_jtag.TDI) - PULLUP(th.jd_4) + IOBUF(th.jd_4, io_jtag.TDI) + PULLUP(th.jd_4) - IOBUF(th.jd_0, io_jtag.TDO) + IOBUF(th.jd_0, io_jtag.TDO) - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) + // mimic putting a pullup on this line (part of reset vote) + th.SRST_n := IOBUF(th.jd_6) + PULLUP(th.jd_6) - // ignore the po input - io_jtag.TCK.i.po.map(_ := DontCare) - io_jtag.TDI.i.po.map(_ := DontCare) - io_jtag.TMS.i.po.map(_ := DontCare) - io_jtag.TDO.i.po.map(_ := DontCare) - } + // ignore the po input + io_jtag.TCK.i.po.map(_ := DontCare) + io_jtag.TDI.i.po.map(_ := DontCare) + io_jtag.TMS.i.po.map(_ := DontCare) + io_jtag.TDO.i.po.map(_ := DontCare) + } } } }) diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala index 78a1f0ee..db656752 100644 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -3,8 +3,7 @@ package chipyard.fpga.arty import chisel3._ import chisel3.experimental.{IO} -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp} import chipyard.iobinders.{ComposeIOBinder} diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index 7acb2bb9..07a96cfd 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -33,12 +33,11 @@ class WithSystemModifications extends Config((site, here, up) => { require (make.! == 0, "Failed to build bootrom") p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin") } - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size (note the size) case SerialTLKey => None // remove serialized tl port }) -// DOC include start: AbstractVC707 and Rocket -class WithVC707Tweaks extends Config( +class WithVC707Tweaks extends Config ( // harness binders new WithVC707UARTHarnessBinder ++ new WithVC707SPISDCardHarnessBinder ++ @@ -57,17 +56,18 @@ class WithVC707Tweaks extends Config( new WithFPGAFrequency(50) // default 50MHz freq ) -class RocketVC707Config extends Config( +class RocketVC707Config extends Config ( new WithVC707Tweaks ++ - new chipyard.RocketConfig) -// DOC include end: AbstractVC707 and Rocket + new chipyard.RocketConfig +) -class BoomVC707Config extends Config( +class BoomVC707Config extends Config ( new WithFPGAFrequency(50) ++ new WithVC707Tweaks ++ - new chipyard.MegaBoomConfig) + new chipyard.MegaBoomConfig +) -class WithFPGAFrequency(fMHz: Double) extends Config( +class WithFPGAFrequency(fMHz: Double) extends Config ( new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. new chipyard.config.WithMemoryBusFrequency(fMHz) ) diff --git a/fpga/src/main/scala/vc707/HarnessBinders.scala b/fpga/src/main/scala/vc707/HarnessBinders.scala index 76bb64eb..cf5bbb5e 100644 --- a/fpga/src/main/scala/vc707/HarnessBinders.scala +++ b/fpga/src/main/scala/vc707/HarnessBinders.scala @@ -43,4 +43,4 @@ class WithVC707DDRMemHarnessBinder extends OverrideHarnessBinder({ ddrClientBundle <> ports.head }} } -}) \ No newline at end of file +}) diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 329c0018..a7f571c8 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -24,10 +24,8 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She def dp = designParameters - // Order matters; ddr depends on sys_clock val uart = Overlay(UARTOverlayKey, new UARTVC707ShellPlacer(this, UARTShellInput())) - val pcie = Overlay(PCIeOverlayKey, new PCIeVC707ShellPlacer(this, PCIeShellInput())) val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") @@ -63,6 +61,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb)) /*** DDR ***/ + // Modify the last field of `DDRDesignInput` for 1GB RAM size val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL, true)).overlayOutput.ddr @@ -90,9 +89,6 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul resetIBUF.io.I := reset val sysclk: Clock = _outer.sysClkNode.out.head._1.clock - // val sysclk: Clock = sys_clock.get() match { - // case Some(x: SysClockVC707PlacedOverlay) => x.clock - // } val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk) _outer.sdc.addAsyncPath(Seq(powerOnReset)) @@ -124,4 +120,4 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul // check the top-level reference clock is equal to the default // non-exhaustive since you need all ChipTop clocks to equal the default require(getRefClockFreq == p(DefaultClockFrequencyKey)) -} \ No newline at end of file +} diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 47a22dcf..6c8cb3a6 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -60,13 +60,15 @@ class WithVCU118Tweaks extends Config( class RocketVCU118Config extends Config( new WithVCU118Tweaks ++ - new chipyard.RocketConfig) + new chipyard.RocketConfig +) // DOC include end: AbstractVCU118 and Rocket class BoomVCU118Config extends Config( new WithFPGAFrequency(50) ++ new WithVCU118Tweaks ++ - new chipyard.MegaBoomConfig) + new chipyard.MegaBoomConfig +) class WithFPGAFrequency(fMHz: Double) extends Config( new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq. diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index ab6897c9..90ce51e0 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -3,19 +3,17 @@ package chipyard.fpga.vcu118 import chisel3._ import chisel3.experimental.{IO} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink._ +import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource} +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.tilelink.{TLClientNode} -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.ip.xilinx._ -import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks._ +import sifive.fpgashells.shell.xilinx.{VCU118ShellBasicOverlays, UARTVCU118ShellPlacer, SDIOVCU118ShellPlacer, JTAGDebugBScanVCU118ShellPlacer, JTAGDebugVCU118ShellPlacer, cJTAGDebugVCU118ShellPlacer, PCIeVCU118FMCShellPlacer, PCIeVCU118EdgeShellPlacer, VCU118ShellPMOD, ChipLinkVCU118PlacedOverlay} +import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} +import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, ClockInputShellInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, SPIOverlayKey, SPIDesignInput, SPIShellInput, JTAGDebugOverlayKey, JTAGDebugShellInput, JTAGDebugBScanOverlayKey, JTAGDebugBScanShellInput, cJTAGDebugOverlayKey, cJTAGDebugShellInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput, DDRShellInput} +import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler} -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO} +import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO} import chipyard.{HasHarnessSignalReferences, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey} import chipyard.iobinders.{HasIOBinders}