Clean up code

2022-11-30 16:56:09 +09:00
parent a2d1f16488
commit 0724431873
8 changed files with 59 additions and 63 deletions
--- a/fpga/src/main/scala/vc707/HarnessBinders.scala
+++ b/fpga/src/main/scala/vc707/HarnessBinders.scala
@@ -43,4 +43,4 @@ class WithVC707DDRMemHarnessBinder extends OverrideHarnessBinder({
      ddrClientBundle <> ports.head
    }}
  }
-})
+})