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Clean up code

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This commit is contained in:
Lori Li
2022-11-30 16:56:09 +09:00
parent a2d1f16488
commit 0724431873
8 changed files with 59 additions and 63 deletions
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18
fpga/src/main/scala/vc707/Configs.scala
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@@ -33,12 +33,11 @@ class WithSystemModifications extends Config((site, here, up) => {
require (make.! == 0, "Failed to build bootrom")
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin")
}
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size (note the size)
case SerialTLKey => None // remove serialized tl port
})
// DOC include start: AbstractVC707 and Rocket
class WithVC707Tweaks extends Config(
class WithVC707Tweaks extends Config (
// harness binders
new WithVC707UARTHarnessBinder ++
new WithVC707SPISDCardHarnessBinder ++
@@ -57,17 +56,18 @@ class WithVC707Tweaks extends Config(
new WithFPGAFrequency(50) // default 50MHz freq
)
class RocketVC707Config extends Config(
class RocketVC707Config extends Config (
new WithVC707Tweaks ++
new chipyard.RocketConfig)
// DOC include end: AbstractVC707 and Rocket
new chipyard.RocketConfig
)
class BoomVC707Config extends Config(
class BoomVC707Config extends Config (
new WithFPGAFrequency(50) ++
new WithVC707Tweaks ++
new chipyard.MegaBoomConfig)
new chipyard.MegaBoomConfig
)
class WithFPGAFrequency(fMHz: Double) extends Config(
class WithFPGAFrequency(fMHz: Double) extends Config (
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
new chipyard.config.WithMemoryBusFrequency(fMHz)
)

2
fpga/src/main/scala/vc707/HarnessBinders.scala
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@@ -43,4 +43,4 @@ class WithVC707DDRMemHarnessBinder extends OverrideHarnessBinder({
ddrClientBundle <> ports.head
}}
}
})
})

8
fpga/src/main/scala/vc707/TestHarness.scala
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@@ -24,10 +24,8 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
def dp = designParameters
// Order matters; ddr depends on sys_clock
val uart = Overlay(UARTOverlayKey, new UARTVC707ShellPlacer(this, UARTShellInput()))
val pcie = Overlay(PCIeOverlayKey, new PCIeVC707ShellPlacer(this, PCIeShellInput()))
val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
@@ -63,6 +61,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb))
/*** DDR ***/
// Modify the last field of `DDRDesignInput` for 1GB RAM size
val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL, true)).overlayOutput.ddr
@@ -90,9 +89,6 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
resetIBUF.io.I := reset
val sysclk: Clock = _outer.sysClkNode.out.head._1.clock
// val sysclk: Clock = sys_clock.get() match {
// case Some(x: SysClockVC707PlacedOverlay) => x.clock
// }
val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
_outer.sdc.addAsyncPath(Seq(powerOnReset))
@@ -124,4 +120,4 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
// check the top-level reference clock is equal to the default
// non-exhaustive since you need all ChipTop clocks to equal the default
require(getRefClockFreq == p(DefaultClockFrequencyKey))
}
}