Merge branch 'add-disallowPackedArrays' of https://github.com/ucb-bar/chipyard into add-disallowPackedArrays

.github/scripts/check-commit.sh

@@ -88,7 +88,7 @@ dir="software"
 branches=("master" "dev")
 search
 
-submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "rocket-dsp-utils" "torture")
+submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture")
 dir="tools"
 branches=("master" "dev")
 search

.github/workflows/chipyard-full-flow.yml

@@ -81,6 +81,19 @@ jobs:
           export MAKEFLAGS="-j32"
           ./build-setup.sh -f
 
+  run-cfg-finder:
+    name: run-cfg-finder
+    needs: [setup-repo]
+    runs-on: ferry
+    steps:
+      - name: Run config finder
+        run: |
+          cd ${{ env.REMOTE_WORK_DIR }}
+          eval "$(conda shell.bash hook)"
+          source env.sh
+          cd sims/verilator
+          make find-config-fragments
+
   run-tutorial:
     name: run-tutorial
     needs: [setup-repo]

.gitmodules

@@ -31,9 +31,6 @@
 [submodule "tools/dsptools"]
 	path = tools/dsptools
 	url = https://github.com/ucb-bar/dsptools.git
-[submodule "tools/chisel-testers"]
-	path = tools/chisel-testers
-	url = https://github.com/freechipsproject/chisel-testers.git
 [submodule "generators/sha3"]
 	path = generators/sha3
 	url = https://github.com/ucb-bar/sha3.git

common.mk

@@ -29,10 +29,6 @@ EXTRA_SIM_SOURCES    ?=
 EXTRA_SIM_REQS       ?=
 ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_VLSI_FLOW)
 
-
-$(info $$ENABLE_CUSTOM_FIRRTL_PASS is [${ENABLE_CUSTOM_FIRRTL_PASS}])
-$(info $$ENABLE_VLSI_FLOW is [${ENABLE_VLSI_FLOW}])
-
 #----------------------------------------------------------------------------
 HELP_SIMULATION_VARIABLES += \
 "   EXTRA_SIM_FLAGS        = additional runtime simulation flags (passed within +permissive)" \
@@ -54,6 +50,7 @@ HELP_COMMANDS += \
 "   run-tests                   = run all assembly and benchmark tests" \
 "   launch-sbt                  = start sbt terminal" \
 "   {shutdown,start}-sbt-server = shutdown or start sbt server if using ENABLE_SBT_THIN_CLIENT" \
+"   find-config-fragments       = list all config. fragments and their locations (recursive up to CONFIG_FRAG_LEVELS=$(CONFIG_FRAG_LEVELS))"
 
 #########################################################################################
 # include additional subproject make fragments
@@ -164,6 +161,7 @@ SFC_MFC_TARGETS = \
 	$(GEN_COLLATERAL_DIR)
 
 SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
+MFC_BASE_LOWERING_OPTIONS = emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket
 
 # DOC include start: FirrtlCompiler
 # There are two possible cases for this step. In the first case, SFC
@@ -176,13 +174,18 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
 # hack: lower to low firrtl if Fixed types are found
 # hack: when using dontTouch, io.cpu annotations are not removed by SFC,
 # hence we remove them manually by using jq before passing them to firtool
-$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE)
+$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE)
 ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
 	$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none))
 	$(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),))
 else
 	$(eval SFC_LEVEL := low)
 	$(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM))
+endif
+ifeq (,$(ENABLE_VLSI_FLOW))
+	$(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS))
+else
+	$(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays)
 endif
 	if [ $(SFC_LEVEL) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
 	if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
@@ -214,7 +217,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LE
 		--disable-annotation-classless \
 		--disable-annotation-unknown \
 		--mlir-timing \
-		--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,disallowPackedArrays,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
+		--lowering-options=$(MFC_LOWERING_OPTIONS) \
 		--repl-seq-mem \
 		--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
 		--repl-seq-mem-circuit=$(MODEL) \
@@ -393,8 +396,21 @@ start-sbt-server: check-thin-client
 	cd $(base_dir) && $(SBT) "exit"
 
 #########################################################################################
-# print help text
+# print help text (and other help)
 #########################################################################################
+# helper to add newlines (avoid bash argument too long)
+define \n
+
+
+endef
+
+CONFIG_FRAG_LEVELS ?= 3
+.PHONY: find-config-fragments
+find-config-fragments: $(SCALA_SOURCES)
+	rm -rf /tmp/scala_files.f
+	@$(foreach file,$(SCALA_SOURCES),echo $(file) >> /tmp/scala_files.f${\n})
+	$(base_dir)/scripts/config-finder.py -l $(CONFIG_FRAG_LEVELS) /tmp/scala_files.f
+
 .PHONY: help
 help:
 	@for line in $(HELP_LINES); do echo "$$line"; done

docs/Customization/Keys-Traits-Configs.rst

@@ -75,3 +75,9 @@ We can use this config fragment when composing our configs.
 
 .. note::
    Readers who want more information on the configuration system may be interested in reading :ref:`cdes`.
+
+Chipyard Config Fragments
+-------------------------
+
+For discoverability, users can run ``make find-config-fragments`` to see a list of config. fragments
+(config. fragments that match "class NAME extends CONFIG\n" on a single line and a subset of their children) and their file path in a fully initialized Chipyard repository.

docs/Tools/Chisel-Testers.rst

@@ -1,7 +0,0 @@
-Chisel Testers
-==============================
-
-`Chisel Testers <https://github.com/freechipsproject/chisel-testers>`__ is a library for writing tests for Chisel designs.
-It provides a Scala API for interacting with a DUT.
-It can use multiple backends, including things such as Treadle and Verilator.
-See :ref:`Tools/Treadle:Treadle and FIRRTL Interpreter` and :ref:`sw-rtl-sim-intro` for more information on these simulation methods.

docs/Tools/index.rst

@@ -11,7 +11,6 @@ The following pages will introduce them, and how we can use them in order to gen
    Chisel
    FIRRTL
    Treadle
-   Chisel-Testers
    Dsptools
    Barstools
    Dromajo

scripts/config-finder.py

@@ -0,0 +1,76 @@
+#!/usr/bin/env python3
+
+import argparse
+import subprocess
+from collections import defaultdict
+import re
+from copy import deepcopy
+import os
+
+cy_path = os.path.dirname(os.path.dirname(os.path.realpath(__file__)))
+
+# from https://gist.github.com/angstwad/bf22d1822c38a92ec0a9
+def deep_merge(a: dict, b: dict) -> dict:
+    """Merge two dicts and return a singular dict"""
+    result = deepcopy(a)
+    for bk, bv in b.items():
+        av = result.get(bk)
+        if isinstance(av, dict) and isinstance(bv, dict):
+            result[bk] = deep_merge(av, bv)
+        else:
+            result[bk] = deepcopy(bv)
+    return result
+
+if __name__ == "__main__":
+  parser = argparse.ArgumentParser(description='Pretty print all configs given a filelist of scala files')
+  parser.add_argument('FILE', type=str, help='Filelist of scala files to search within')
+  parser.add_argument('-l', '--levels', default=0, type=int, help='Number of levels to recursively look for configs')
+  args = parser.parse_args()
+
+  files = []
+  with open(args.FILE, 'r') as f:
+    files = f.read().splitlines()
+
+  cmd = ['grep', '-o', r"class \+.* \+extends \+Config"] + files
+  r = subprocess.run(cmd, check=True, capture_output=True)
+
+  base_file_path_dict = defaultdict(list)
+  for l in r.stdout.decode("UTF-8").splitlines():
+    match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l)
+    if match:
+      base_file_path_dict[match.group(1)].append(match.group(2))
+
+  levels = []
+  for level in range(args.levels):
+    if level == 0:
+      # use the base
+      dict_to_use = base_file_path_dict
+    else:
+      # use the level-1 dict
+      assert len(levels) > 0
+      dict_to_use = levels[-1]
+
+    file_path_dict = defaultdict(list)
+
+    for configs in dict_to_use.values():
+      for config in configs:
+        cmd = ['grep', '-o', r"class \+.* \+extends \+" + f"{config}"] + files
+        r = subprocess.run(cmd, capture_output=True)
+
+        for l in r.stdout.decode("UTF-8").splitlines():
+          match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l)
+          if match:
+            file_path_dict[match.group(1)].append(match.group(2))
+
+    levels.append(file_path_dict)
+
+  final_dict = base_file_path_dict
+  for dct in levels:
+    final_dict = deep_merge(final_dict, dct)
+
+  print(f"Finding all one-line config. fragments (up to {args.levels} levels)\n")
+  for k, v in final_dict.items():
+    print(f"{k.replace(cy_path, 'chipyard')}:")
+    for e in v:
+      print(f"  {e}")
+    print("")

vlsi/Makefile

@@ -51,6 +51,8 @@ else
 	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
 endif
 
+ENABLE_VLSI_FLOW ?= 1
+
 #########################################################################################
 # general rules
 #########################################################################################