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Add 2bit-sourceId configs to CoalescerConfigs

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... and add those to run-coalperf.sh

It seemed before that configs with narrower sourceId are more likely to
fail because of more contention between outstanding requests, so test
more of those configs.
This commit is contained in:
Hansung Kim
2023-07-22 15:41:13 -07:00
parent 21a4765866
commit 016f293da1
2 changed files with 57 additions and 4 deletions
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59
generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
View File

@@ -25,7 +25,62 @@ class MemtraceCoreConfig extends Config(
/// Various Configs for perf testing (feel free to delete them later) /// Various Configs for perf testing (feel free to delete them later)
///////////////////////////////////////////////// /////////////////////////////////////////////////
//8 src id section class MemtraceCoreNV64B2IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(64) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV128B2IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(128) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV256B2IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(256) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV512B2IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(512) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)
class MemtraceCoreNV64B8IdConfig extends Config( class MemtraceCoreNV64B8IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
traceHasSource = false) ++ traceHasSource = false) ++
@@ -82,7 +137,6 @@ class MemtraceCoreNV512B8IdConfig extends Config(
new chipyard.config.AbstractConfig new chipyard.config.AbstractConfig
) )
//16 src id section
class MemtraceCoreNV64B16IdConfig extends Config( class MemtraceCoreNV64B16IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
traceHasSource = false) ++ traceHasSource = false) ++
@@ -139,7 +193,6 @@ class MemtraceCoreNV512B16IdConfig extends Config(
new chipyard.config.AbstractConfig new chipyard.config.AbstractConfig
) )
// 32 ids sections
class MemtraceCoreNV64B32IdConfig extends Config( class MemtraceCoreNV64B32IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
traceHasSource = false) ++ traceHasSource = false) ++

2
sims/vcs/run-coalperfs.sh
View File

@@ -8,7 +8,7 @@ fi
set -ex set -ex
configurations=("MemtraceCoreNV64B8IdConfig" "MemtraceCoreNV128B8IdConfig" "MemtraceCoreNV256B8IdConfig" "MemtraceCoreNV64B16IdConfig" "MemtraceCoreNV128B16IdConfig" "MemtraceCoreNV256B16IdConfig" "MemtraceCoreNV64B32IdConfig" "MemtraceCoreNV128B32IdConfig" "MemtraceCoreNV256B32IdConfig") configurations=("MemtraceCoreNV64B2IdConfig" "MemtraceCoreNV128B2IdConfig" "MemtraceCoreNV256B2IdConfig" "MemtraceCoreNV64B8IdConfig" "MemtraceCoreNV128B8IdConfig" "MemtraceCoreNV256B8IdConfig" "MemtraceCoreNV64B16IdConfig" "MemtraceCoreNV128B16IdConfig" "MemtraceCoreNV256B16IdConfig" "MemtraceCoreNV64B32IdConfig" "MemtraceCoreNV128B32IdConfig" "MemtraceCoreNV256B32IdConfig")
# Disabled as Chipyard fails to elaborate with 512b sbus: # Disabled as Chipyard fails to elaborate with 512b sbus:
# "MemtraceCoreNV512B8IdConfig" "MemtraceCoreNV512B16IdConfig" "MemtraceCoreNV512B32IdConfig" # "MemtraceCoreNV512B8IdConfig" "MemtraceCoreNV512B16IdConfig" "MemtraceCoreNV512B32IdConfig"