diff --git a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
index c035e3cf..34cce07e 100644
--- a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
@@ -25,7 +25,62 @@ class MemtraceCoreConfig extends Config(
 /// Various Configs for perf testing (feel free to delete them later)
 /////////////////////////////////////////////////
 
-//8 src id section
+class MemtraceCoreNV64B2IdConfig extends Config(
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++
+  new chipyard.config.WithSystemBusWidth(64) ++
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+class MemtraceCoreNV128B2IdConfig extends Config(
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+class MemtraceCoreNV256B2IdConfig extends Config(
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++
+  new chipyard.config.WithSystemBusWidth(256) ++
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+class MemtraceCoreNV512B2IdConfig extends Config(
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=2) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++
+  new chipyard.config.WithSystemBusWidth(512) ++
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
 class MemtraceCoreNV64B8IdConfig extends Config(
   new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
   traceHasSource = false) ++
@@ -82,7 +137,6 @@ class MemtraceCoreNV512B8IdConfig extends Config(
   new chipyard.config.AbstractConfig
   )
 
-//16 src id section
 class MemtraceCoreNV64B16IdConfig extends Config(
   new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
   traceHasSource = false) ++
@@ -139,7 +193,6 @@ class MemtraceCoreNV512B16IdConfig extends Config(
   new chipyard.config.AbstractConfig
   )
 
-// 32 ids sections
 class MemtraceCoreNV64B32IdConfig extends Config(
   new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
   traceHasSource = false) ++
diff --git a/sims/vcs/run-coalperfs.sh b/sims/vcs/run-coalperfs.sh
index 19756ffe..797c399d 100755
--- a/sims/vcs/run-coalperfs.sh
+++ b/sims/vcs/run-coalperfs.sh
@@ -8,7 +8,7 @@ fi
 
 set -ex
 
-configurations=("MemtraceCoreNV64B8IdConfig" "MemtraceCoreNV128B8IdConfig" "MemtraceCoreNV256B8IdConfig" "MemtraceCoreNV64B16IdConfig" "MemtraceCoreNV128B16IdConfig" "MemtraceCoreNV256B16IdConfig" "MemtraceCoreNV64B32IdConfig" "MemtraceCoreNV128B32IdConfig" "MemtraceCoreNV256B32IdConfig") 
+configurations=("MemtraceCoreNV64B2IdConfig" "MemtraceCoreNV128B2IdConfig" "MemtraceCoreNV256B2IdConfig" "MemtraceCoreNV64B8IdConfig" "MemtraceCoreNV128B8IdConfig" "MemtraceCoreNV256B8IdConfig" "MemtraceCoreNV64B16IdConfig" "MemtraceCoreNV128B16IdConfig" "MemtraceCoreNV256B16IdConfig" "MemtraceCoreNV64B32IdConfig" "MemtraceCoreNV128B32IdConfig" "MemtraceCoreNV256B32IdConfig") 
 # Disabled as Chipyard fails to elaborate with 512b sbus:
 # "MemtraceCoreNV512B8IdConfig" "MemtraceCoreNV512B16IdConfig" "MemtraceCoreNV512B32IdConfig"