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async to rational crossings

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alonamid
2021-06-07 21:13:10 -07:00
parent 610adfc3f7
commit 014c19768d
1 changed files with 2 additions and 2 deletions
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4
generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -330,7 +330,7 @@ class WithTestChipBusFreqs extends Config(
// Crossing specifications // Crossing specifications
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(4,4) ++ // Add Async crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new boom.common.WithAsynchronousBoomTiles ++ // Add Async crossings between BoomTile and uncore new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new testchipip.WithAsynchronousSerialSlaveCrossing // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new testchipip.WithAsynchronousSerialSlaveCrossing // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
) )