From 014c19768d63de0ee1977d0a9890d172af170024 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 7 Jun 2021 21:13:10 -0700 Subject: [PATCH] async to rational crossings --- generators/chipyard/src/main/scala/ConfigFragments.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 0e07b038..7e5042b8 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -330,7 +330,7 @@ class WithTestChipBusFreqs extends Config( // Crossing specifications new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(4,4) ++ // Add Async crossings between RocketTile and uncore - new boom.common.WithAsynchronousBoomTiles ++ // Add Async crossings between BoomTile and uncore + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore new testchipip.WithAsynchronousSerialSlaveCrossing // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS )