Merge remote-tracking branch 'origin' into symmetric_sertl

fpga/src/main/scala/arty100t/Configs.scala

@@ -21,9 +21,13 @@ class WithNoDesignKey extends Config((site, here, up) => {
   case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
 })
 
+// By default, this uses the on-board USB-UART for the TSI-over-UART link
+// The PMODUART HarnessBinder maps the actual UART device to JD pin
 class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
+  new WithArty100TPMODUART ++
   new WithArty100TUARTTSI ++
   new WithArty100TDDRTL ++
+  new WithArty100TJTAG ++
   new WithNoDesignKey ++
   new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
@@ -36,14 +40,13 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.config.WithNoDebug ++ // no jtag
-  new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
   new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
   new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
   new freechips.rocketchip.subsystem.WithoutTLMonitors)
 
 class RocketArty100TConfig extends Config(
   new WithArty100TTweaks ++
+  new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 128 * 1024) ++ // add on-chip scratchpad for small programs
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.RocketConfig)
 

fpga/src/main/scala/arty100t/Harness.scala

@@ -33,9 +33,6 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
 
   harnessSysPLLNode := clockOverlay.overlayOutput.node
 
-  val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
-  val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
-
   val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
   val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
     name = "chip_ddr",

fpga/src/main/scala/arty100t/HarnessBinders.scala

@@ -24,7 +24,17 @@ import testchipip.serdes._
 class WithArty100TUARTTSI extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
-    ath.io_uart_bb.bundle <> port.io.uart
+    val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
+    harnessIO <> port.io.uart
+    val packagePinsWithPackageIOs = Seq(
+      ("A9" , IOPin(harnessIO.rxd)),
+      ("D10", IOPin(harnessIO.txd)))
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addIOB(io)
+    } }
+
     ath.other_leds(1) := port.io.dropped
     ath.other_leds(9) := port.io.tsi2tl_state(0)
     ath.other_leds(10) := port.io.tsi2tl_state(1)
@@ -33,6 +43,7 @@ class WithArty100TUARTTSI extends HarnessBinder({
   }
 })
 
+
 class WithArty100TDDRTL extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
     val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
@@ -93,3 +104,46 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
     }
   }
 })
+
+// Maps the UART device to the on-board USB-UART
+class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: UARTPort) => {
+    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
+    harnessIO <> port.io
+    val packagePinsWithPackageIOs = Seq(
+      (rxdPin, IOPin(harnessIO.rxd)),
+      (txdPin, IOPin(harnessIO.txd)))
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addIOB(io)
+    } }
+  }
+})
+
+// Maps the UART device to PMOD JD pins 3/7
+class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
+
+class WithArty100TJTAG extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: JTAGPort) => {
+    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
+    harnessIO <> port.io
+
+    ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
+    ath.sdc.addGroup(clocks = Seq("JTCK"))
+    ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK))
+    val packagePinsWithPackageIOs = Seq(
+      ("F4", IOPin(harnessIO.TCK)),
+      ("D2", IOPin(harnessIO.TMS)),
+      ("E2", IOPin(harnessIO.TDI)),
+      ("D4", IOPin(harnessIO.TDO))
+    )
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addPullup(io)
+    } }
+  }
+})

generators/chipyard/src/main/scala/iobinders/IOBinders.scala

@@ -116,7 +116,10 @@ object GetSystemParameters {
 }
 
 class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
-  case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> composer(up(IOBinders, site)(tag.runtimeClass.toString)))
+  case IOBinders => {
+    val upMap = up(IOBinders)
+    upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString)))
+  }
 })
 
 class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](

scripts/build-setup.sh

@@ -29,7 +29,8 @@ usage() {
     echo "   7. FireSim pre-compile sources"
     echo "   8. FireMarshal"
     echo "   9. FireMarshal pre-compile default buildroot Linux sources"
-    echo "  10. Runs repository clean-up"
+    echo "  10. Install CIRCT"
+    echo "  11. Runs repository clean-up"
     echo ""
     echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**"
     echo ""
@@ -152,16 +153,6 @@ if run_step "1"; then
     conda activate $CYDIR/.conda-env
     exit_if_last_command_failed
 
-    # install circt into conda
-    git submodule update --init $CYDIR/tools/install-circt &&
-    $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
-        -f circt-full-shared-linux-x64.tar.gz \
-        -i $CONDA_PREFIX \
-        -v version-file \
-        -x $CYDIR/conda-reqs/circt.json \
-        -g null
-    exit_if_last_command_failed
-
     # Conda Setup
     # Provide a sourceable snippet that can be used in subshells that may not have
     # inhereted conda functions that would be brought in under a login shell that
@@ -273,8 +264,31 @@ if run_step "8"; then
     popd
 fi
 
-# do misc. cleanup for a "clean" git status
 if run_step "10"; then
+    # install circt into conda
+    if run_step "1"; then
+        PREFIX=$CONDA_PREFIX/$TOOLCHAIN_TYPE
+    else
+        if [ -z "$RISCV" ] ; then
+            error "ERROR: If conda initialization skipped, \$RISCV variable must be defined."
+            exit 1
+        fi
+        PREFIX=$RISCV
+    fi
+
+    git submodule update --init $CYDIR/tools/install-circt &&
+    $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
+        -f circt-full-shared-linux-x64.tar.gz \
+        -i $PREFIX \
+        -v version-file \
+        -x $CYDIR/conda-reqs/circt.json \
+        -g null
+    exit_if_last_command_failed
+fi
+
+
+# do misc. cleanup for a "clean" git status
+if run_step "11"; then
     begin_step "10" "Cleaning up repository"
     $CYDIR/scripts/repo-clean.sh
     exit_if_last_command_failed