hexu
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  • Joined on 2025-12-08
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hexu pushed to wu-blackwell-4lane-tc at wu-arch/radiance 2026-05-27 16:47:41 +08:00
1e78574113 Fix Blackwell SMEM fragment alignment
hexu pushed to wu-blackwell-4lane-tc at wu-arch/chipyard 2026-05-27 13:57:17 +08:00
3cb58af336 Update radiance for 4-lane Blackwell tensor core
hexu created branch wu-blackwell-4lane-tc in wu-arch/chipyard 2026-05-27 13:57:17 +08:00
hexu pushed to wu-blackwell-4lane-tc at wu-arch/kernels 2026-05-27 13:57:01 +08:00
ed16541c8e Use 16-byte fragments in wu_arch_hgemm
hexu created branch wu-blackwell-4lane-tc in wu-arch/kernels 2026-05-27 13:57:01 +08:00
hexu pushed to wu-blackwell-4lane-tc at wu-arch/radiance 2026-05-27 13:56:44 +08:00
c6c30ec0dc Add 4-lane Blackwell tensor core support
hexu created branch wu-blackwell-4lane-tc in wu-arch/radiance 2026-05-27 13:56:44 +08:00
hexu pushed to wu-blackwell-4lane-tc at wu-arch/vortex 2026-05-27 13:56:38 +08:00
abee301b6e Support 4-lane Blackwell tensor wrapper
hexu created branch wu-blackwell-4lane-tc in wu-arch/vortex 2026-05-27 13:56:29 +08:00
hexu pushed to ae at wu-arch/kernels 2026-05-27 09:16:56 +08:00
122a048ea6 Add WU architecture kernel cases
hexu pushed to wu-architecture at wu-arch/chipyard 2026-05-27 09:16:39 +08:00
87783dc9f6 Track radiance WU architecture updates
hexu pushed to wu-architecture at wu-arch/radiance 2026-05-27 09:16:20 +08:00
126523c5d2 Track vortex masked barrier fix
hexu pushed to wu-architecture at wu-arch/vortex 2026-05-27 09:15:59 +08:00
c87fea5c48 Keep masked barriers local under cluster gbar
hexu pushed to ae at wu-arch/kernels 2026-05-26 21:00:38 +08:00
9f4be1b8f7 Update Wu architecture kernel implementations and runtime library
hexu pushed to wu-architecture at wu-arch/chipyard 2026-05-26 21:00:24 +08:00
9206c4452f Update submodules and gitmodules configuration
5ce98e1491 Update WU architecture integration
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hexu pushed to wu-architecture at wu-arch/vortex 2026-05-25 19:44:45 +08:00
0ad87bde81 Implement WU architecture support
323ed7d7e9 Update Vortex core for Blackwell tensor instructions
cb912d3b8b Add Blackwell tensor RTL scaffolding
f1d0fac518 Change to 8-core Volta/Ampere config
c8529c4339 Disable EXT_T_HOPPER atm for flash runs
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hexu created branch wu-architecture in wu-arch/vortex 2026-05-25 19:44:45 +08:00
hexu pushed to master at wu-arch/vortex 2026-05-25 19:44:45 +08:00
2f4fd11c93 Add vecadd-loop
6563ed696e Force per-global-thread stack allocation
92ed21f83f [driver] Set different base address for device malloc
46a60cf58e [driver] Fix bug in addr range check for upload/download
6ffb8c37e9 [tests] Make an args.bin copy in vecadd Makefile
Compare 10 commits »
hexu created branch master in wu-arch/vortex 2026-05-25 19:44:45 +08:00
hexu pushed to wu-architecture at wu-arch/radiance 2026-05-25 19:40:38 +08:00
87a4bbc757 Integrate WU architecture in Radiance
5112f3665a Add Blackwell tensor core implementation and tests
136cf70a58 Add Blackwell tensor core baseline plumbing
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