3007 lines
145 KiB
Systemverilog
3007 lines
145 KiB
Systemverilog
// Generated by CIRCT firtool-1.139.0
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module ReservationStation(
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input clock,
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reset,
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io_enqValid_0,
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io_enqValid_1,
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input [63:0] io_enq_0_decoded_pc,
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input [31:0] io_enq_0_decoded_inst,
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input [4:0] io_enq_0_decoded_rs1,
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io_enq_0_decoded_rs2,
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input [2:0] io_enq_0_decoded_funct3,
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input [63:0] io_enq_0_decoded_immI,
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io_enq_0_decoded_immS,
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io_enq_0_decoded_immB,
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io_enq_0_decoded_immU,
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io_enq_0_decoded_immJ,
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input [4:0] io_enq_0_decoded_aluFn,
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input [2:0] io_enq_0_decoded_memWidth,
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input io_enq_0_decoded_isLoad,
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io_enq_0_decoded_isStore,
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io_enq_0_decoded_isBranch,
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io_enq_0_decoded_isJal,
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io_enq_0_decoded_isJalr,
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io_enq_0_decoded_isLui,
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io_enq_0_decoded_isAuipc,
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io_enq_0_decoded_isOpImm,
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io_enq_0_decoded_isWord,
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io_enq_0_decoded_isSystem,
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io_enq_0_decoded_writesRd,
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io_enq_0_decoded_illegal,
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input [5:0] io_enq_0_prs1,
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io_enq_0_prs2,
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input io_enq_0_src1Ready,
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io_enq_0_src2Ready,
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input [5:0] io_enq_0_prd,
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io_enq_0_robIdx,
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input [63:0] io_enq_1_decoded_pc,
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input [31:0] io_enq_1_decoded_inst,
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input [4:0] io_enq_1_decoded_rs1,
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io_enq_1_decoded_rs2,
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input [2:0] io_enq_1_decoded_funct3,
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input [63:0] io_enq_1_decoded_immI,
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io_enq_1_decoded_immS,
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io_enq_1_decoded_immB,
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io_enq_1_decoded_immU,
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io_enq_1_decoded_immJ,
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input [4:0] io_enq_1_decoded_aluFn,
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input [2:0] io_enq_1_decoded_memWidth,
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input io_enq_1_decoded_isLoad,
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io_enq_1_decoded_isStore,
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io_enq_1_decoded_isBranch,
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io_enq_1_decoded_isJal,
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io_enq_1_decoded_isJalr,
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io_enq_1_decoded_isLui,
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io_enq_1_decoded_isAuipc,
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io_enq_1_decoded_isOpImm,
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io_enq_1_decoded_isWord,
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io_enq_1_decoded_isSystem,
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io_enq_1_decoded_writesRd,
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io_enq_1_decoded_illegal,
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input [5:0] io_enq_1_prs1,
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io_enq_1_prs2,
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input io_enq_1_src1Ready,
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io_enq_1_src2Ready,
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input [5:0] io_enq_1_prd,
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io_enq_1_robIdx,
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output io_enqReady_0,
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io_enqReady_1,
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input io_wakeup_0_valid,
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input [5:0] io_wakeup_0_phys,
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input io_wakeup_1_valid,
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input [5:0] io_wakeup_1_phys,
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output io_issueValid_0,
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io_issueValid_1,
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output [63:0] io_issue_0_decoded_pc,
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output [31:0] io_issue_0_decoded_inst,
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output [4:0] io_issue_0_decoded_rs1,
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output [2:0] io_issue_0_decoded_funct3,
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output [63:0] io_issue_0_decoded_immI,
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io_issue_0_decoded_immS,
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io_issue_0_decoded_immB,
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io_issue_0_decoded_immU,
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io_issue_0_decoded_immJ,
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output [4:0] io_issue_0_decoded_aluFn,
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output [2:0] io_issue_0_decoded_memWidth,
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output io_issue_0_decoded_isLoad,
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io_issue_0_decoded_isStore,
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io_issue_0_decoded_isBranch,
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io_issue_0_decoded_isJal,
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io_issue_0_decoded_isJalr,
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io_issue_0_decoded_isLui,
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io_issue_0_decoded_isAuipc,
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io_issue_0_decoded_isOpImm,
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io_issue_0_decoded_isWord,
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io_issue_0_decoded_isSystem,
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io_issue_0_decoded_writesRd,
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io_issue_0_decoded_illegal,
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output [5:0] io_issue_0_prs1,
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io_issue_0_prs2,
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io_issue_0_prd,
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io_issue_0_robIdx,
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output [63:0] io_issue_1_decoded_pc,
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output [31:0] io_issue_1_decoded_inst,
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output [4:0] io_issue_1_decoded_rs1,
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output [2:0] io_issue_1_decoded_funct3,
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output [63:0] io_issue_1_decoded_immI,
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io_issue_1_decoded_immS,
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io_issue_1_decoded_immB,
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io_issue_1_decoded_immU,
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io_issue_1_decoded_immJ,
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output [4:0] io_issue_1_decoded_aluFn,
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output [2:0] io_issue_1_decoded_memWidth,
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output io_issue_1_decoded_isLoad,
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io_issue_1_decoded_isStore,
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io_issue_1_decoded_isBranch,
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io_issue_1_decoded_isJal,
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io_issue_1_decoded_isJalr,
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io_issue_1_decoded_isLui,
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io_issue_1_decoded_isAuipc,
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io_issue_1_decoded_isOpImm,
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io_issue_1_decoded_isWord,
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io_issue_1_decoded_isSystem,
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io_issue_1_decoded_writesRd,
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io_issue_1_decoded_illegal,
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output [5:0] io_issue_1_prs1,
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io_issue_1_prs2,
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io_issue_1_prd,
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io_issue_1_robIdx,
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input io_issueReady_0,
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io_issueReady_1,
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io_flush
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);
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reg valid_0;
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reg valid_1;
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reg valid_2;
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reg valid_3;
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reg valid_4;
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reg valid_5;
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reg valid_6;
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reg valid_7;
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reg valid_8;
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reg valid_9;
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reg valid_10;
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reg valid_11;
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reg valid_12;
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reg valid_13;
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reg valid_14;
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reg valid_15;
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reg [63:0] slots_0_decoded_pc;
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reg [31:0] slots_0_decoded_inst;
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reg [4:0] slots_0_decoded_rs1;
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reg [4:0] slots_0_decoded_rs2;
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reg [2:0] slots_0_decoded_funct3;
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reg [63:0] slots_0_decoded_immI;
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reg [63:0] slots_0_decoded_immS;
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reg [63:0] slots_0_decoded_immB;
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reg [63:0] slots_0_decoded_immU;
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reg [63:0] slots_0_decoded_immJ;
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reg [4:0] slots_0_decoded_aluFn;
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reg [2:0] slots_0_decoded_memWidth;
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reg slots_0_decoded_isLoad;
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reg slots_0_decoded_isStore;
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reg slots_0_decoded_isBranch;
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reg slots_0_decoded_isJal;
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reg slots_0_decoded_isJalr;
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reg slots_0_decoded_isLui;
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reg slots_0_decoded_isAuipc;
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reg slots_0_decoded_isOpImm;
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reg slots_0_decoded_isWord;
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reg slots_0_decoded_isSystem;
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reg slots_0_decoded_writesRd;
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reg slots_0_decoded_illegal;
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reg [5:0] slots_0_prs1;
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reg [5:0] slots_0_prs2;
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reg slots_0_src1Ready;
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reg slots_0_src2Ready;
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reg [5:0] slots_0_prd;
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reg [5:0] slots_0_robIdx;
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reg [63:0] slots_1_decoded_pc;
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reg [31:0] slots_1_decoded_inst;
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reg [4:0] slots_1_decoded_rs1;
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reg [4:0] slots_1_decoded_rs2;
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reg [2:0] slots_1_decoded_funct3;
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reg [63:0] slots_1_decoded_immI;
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reg [63:0] slots_1_decoded_immS;
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reg [63:0] slots_1_decoded_immB;
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reg [63:0] slots_1_decoded_immU;
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reg [63:0] slots_1_decoded_immJ;
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reg [4:0] slots_1_decoded_aluFn;
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reg [2:0] slots_1_decoded_memWidth;
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reg slots_1_decoded_isLoad;
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reg slots_1_decoded_isStore;
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reg slots_1_decoded_isBranch;
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reg slots_1_decoded_isJal;
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reg slots_1_decoded_isJalr;
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reg slots_1_decoded_isLui;
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reg slots_1_decoded_isAuipc;
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reg slots_1_decoded_isOpImm;
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reg slots_1_decoded_isWord;
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reg slots_1_decoded_isSystem;
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reg slots_1_decoded_writesRd;
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reg slots_1_decoded_illegal;
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reg [5:0] slots_1_prs1;
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reg [5:0] slots_1_prs2;
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reg slots_1_src1Ready;
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reg slots_1_src2Ready;
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reg [5:0] slots_1_prd;
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reg [5:0] slots_1_robIdx;
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reg [63:0] slots_2_decoded_pc;
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reg [31:0] slots_2_decoded_inst;
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reg [4:0] slots_2_decoded_rs1;
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reg [4:0] slots_2_decoded_rs2;
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reg [2:0] slots_2_decoded_funct3;
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reg [63:0] slots_2_decoded_immI;
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reg [63:0] slots_2_decoded_immS;
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reg [63:0] slots_2_decoded_immB;
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reg [63:0] slots_2_decoded_immU;
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reg [63:0] slots_2_decoded_immJ;
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reg [4:0] slots_2_decoded_aluFn;
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reg [2:0] slots_2_decoded_memWidth;
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reg slots_2_decoded_isLoad;
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reg slots_2_decoded_isStore;
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reg slots_2_decoded_isBranch;
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reg slots_2_decoded_isJal;
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reg slots_2_decoded_isJalr;
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reg slots_2_decoded_isLui;
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reg slots_2_decoded_isAuipc;
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reg slots_2_decoded_isOpImm;
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reg slots_2_decoded_isWord;
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reg slots_2_decoded_isSystem;
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reg slots_2_decoded_writesRd;
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reg slots_2_decoded_illegal;
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reg [5:0] slots_2_prs1;
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reg [5:0] slots_2_prs2;
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reg slots_2_src1Ready;
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reg slots_2_src2Ready;
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reg [5:0] slots_2_prd;
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reg [5:0] slots_2_robIdx;
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reg [63:0] slots_3_decoded_pc;
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reg [31:0] slots_3_decoded_inst;
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reg [4:0] slots_3_decoded_rs1;
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reg [4:0] slots_3_decoded_rs2;
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reg [2:0] slots_3_decoded_funct3;
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reg [63:0] slots_3_decoded_immI;
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reg [63:0] slots_3_decoded_immS;
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reg [63:0] slots_3_decoded_immB;
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reg [63:0] slots_3_decoded_immU;
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reg [63:0] slots_3_decoded_immJ;
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reg [4:0] slots_3_decoded_aluFn;
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reg [2:0] slots_3_decoded_memWidth;
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reg slots_3_decoded_isLoad;
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reg slots_3_decoded_isStore;
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reg slots_3_decoded_isBranch;
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reg slots_3_decoded_isJal;
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reg slots_3_decoded_isJalr;
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reg slots_3_decoded_isLui;
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reg slots_3_decoded_isAuipc;
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reg slots_3_decoded_isOpImm;
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reg slots_3_decoded_isWord;
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reg slots_3_decoded_isSystem;
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reg slots_3_decoded_writesRd;
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reg slots_3_decoded_illegal;
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reg [5:0] slots_3_prs1;
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reg [5:0] slots_3_prs2;
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reg slots_3_src1Ready;
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reg slots_3_src2Ready;
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reg [5:0] slots_3_prd;
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reg [5:0] slots_3_robIdx;
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reg [63:0] slots_4_decoded_pc;
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reg [31:0] slots_4_decoded_inst;
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reg [4:0] slots_4_decoded_rs1;
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reg [4:0] slots_4_decoded_rs2;
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reg [2:0] slots_4_decoded_funct3;
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reg [63:0] slots_4_decoded_immI;
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reg [63:0] slots_4_decoded_immS;
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reg [63:0] slots_4_decoded_immB;
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reg [63:0] slots_4_decoded_immU;
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reg [63:0] slots_4_decoded_immJ;
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reg [4:0] slots_4_decoded_aluFn;
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reg [2:0] slots_4_decoded_memWidth;
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reg slots_4_decoded_isLoad;
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reg slots_4_decoded_isStore;
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reg slots_4_decoded_isBranch;
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reg slots_4_decoded_isJal;
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reg slots_4_decoded_isJalr;
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reg slots_4_decoded_isLui;
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reg slots_4_decoded_isAuipc;
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reg slots_4_decoded_isOpImm;
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reg slots_4_decoded_isWord;
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reg slots_4_decoded_isSystem;
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reg slots_4_decoded_writesRd;
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reg slots_4_decoded_illegal;
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reg [5:0] slots_4_prs1;
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reg [5:0] slots_4_prs2;
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reg slots_4_src1Ready;
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reg slots_4_src2Ready;
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reg [5:0] slots_4_prd;
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reg [5:0] slots_4_robIdx;
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reg [63:0] slots_5_decoded_pc;
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reg [31:0] slots_5_decoded_inst;
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reg [4:0] slots_5_decoded_rs1;
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reg [4:0] slots_5_decoded_rs2;
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reg [2:0] slots_5_decoded_funct3;
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reg [63:0] slots_5_decoded_immI;
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reg [63:0] slots_5_decoded_immS;
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reg [63:0] slots_5_decoded_immB;
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reg [63:0] slots_5_decoded_immU;
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reg [63:0] slots_5_decoded_immJ;
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reg [4:0] slots_5_decoded_aluFn;
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reg [2:0] slots_5_decoded_memWidth;
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reg slots_5_decoded_isLoad;
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reg slots_5_decoded_isStore;
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reg slots_5_decoded_isBranch;
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reg slots_5_decoded_isJal;
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reg slots_5_decoded_isJalr;
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reg slots_5_decoded_isLui;
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reg slots_5_decoded_isAuipc;
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reg slots_5_decoded_isOpImm;
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reg slots_5_decoded_isWord;
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reg slots_5_decoded_isSystem;
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reg slots_5_decoded_writesRd;
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reg slots_5_decoded_illegal;
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reg [5:0] slots_5_prs1;
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reg [5:0] slots_5_prs2;
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reg slots_5_src1Ready;
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reg slots_5_src2Ready;
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reg [5:0] slots_5_prd;
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reg [5:0] slots_5_robIdx;
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reg [63:0] slots_6_decoded_pc;
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reg [31:0] slots_6_decoded_inst;
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reg [4:0] slots_6_decoded_rs1;
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reg [4:0] slots_6_decoded_rs2;
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reg [2:0] slots_6_decoded_funct3;
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reg [63:0] slots_6_decoded_immI;
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reg [63:0] slots_6_decoded_immS;
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reg [63:0] slots_6_decoded_immB;
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reg [63:0] slots_6_decoded_immU;
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reg [63:0] slots_6_decoded_immJ;
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reg [4:0] slots_6_decoded_aluFn;
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reg [2:0] slots_6_decoded_memWidth;
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reg slots_6_decoded_isLoad;
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reg slots_6_decoded_isStore;
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reg slots_6_decoded_isBranch;
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reg slots_6_decoded_isJal;
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reg slots_6_decoded_isJalr;
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reg slots_6_decoded_isLui;
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reg slots_6_decoded_isAuipc;
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reg slots_6_decoded_isOpImm;
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reg slots_6_decoded_isWord;
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reg slots_6_decoded_isSystem;
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reg slots_6_decoded_writesRd;
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reg slots_6_decoded_illegal;
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reg [5:0] slots_6_prs1;
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reg [5:0] slots_6_prs2;
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reg slots_6_src1Ready;
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reg slots_6_src2Ready;
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reg [5:0] slots_6_prd;
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reg [5:0] slots_6_robIdx;
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reg [63:0] slots_7_decoded_pc;
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reg [31:0] slots_7_decoded_inst;
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reg [4:0] slots_7_decoded_rs1;
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reg [4:0] slots_7_decoded_rs2;
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reg [2:0] slots_7_decoded_funct3;
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reg [63:0] slots_7_decoded_immI;
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reg [63:0] slots_7_decoded_immS;
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reg [63:0] slots_7_decoded_immB;
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reg [63:0] slots_7_decoded_immU;
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reg [63:0] slots_7_decoded_immJ;
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reg [4:0] slots_7_decoded_aluFn;
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reg [2:0] slots_7_decoded_memWidth;
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reg slots_7_decoded_isLoad;
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reg slots_7_decoded_isStore;
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reg slots_7_decoded_isBranch;
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reg slots_7_decoded_isJal;
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reg slots_7_decoded_isJalr;
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reg slots_7_decoded_isLui;
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reg slots_7_decoded_isAuipc;
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reg slots_7_decoded_isOpImm;
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reg slots_7_decoded_isWord;
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reg slots_7_decoded_isSystem;
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reg slots_7_decoded_writesRd;
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reg slots_7_decoded_illegal;
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reg [5:0] slots_7_prs1;
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reg [5:0] slots_7_prs2;
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reg slots_7_src1Ready;
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reg slots_7_src2Ready;
|
|
reg [5:0] slots_7_prd;
|
|
reg [5:0] slots_7_robIdx;
|
|
reg [63:0] slots_8_decoded_pc;
|
|
reg [31:0] slots_8_decoded_inst;
|
|
reg [4:0] slots_8_decoded_rs1;
|
|
reg [4:0] slots_8_decoded_rs2;
|
|
reg [2:0] slots_8_decoded_funct3;
|
|
reg [63:0] slots_8_decoded_immI;
|
|
reg [63:0] slots_8_decoded_immS;
|
|
reg [63:0] slots_8_decoded_immB;
|
|
reg [63:0] slots_8_decoded_immU;
|
|
reg [63:0] slots_8_decoded_immJ;
|
|
reg [4:0] slots_8_decoded_aluFn;
|
|
reg [2:0] slots_8_decoded_memWidth;
|
|
reg slots_8_decoded_isLoad;
|
|
reg slots_8_decoded_isStore;
|
|
reg slots_8_decoded_isBranch;
|
|
reg slots_8_decoded_isJal;
|
|
reg slots_8_decoded_isJalr;
|
|
reg slots_8_decoded_isLui;
|
|
reg slots_8_decoded_isAuipc;
|
|
reg slots_8_decoded_isOpImm;
|
|
reg slots_8_decoded_isWord;
|
|
reg slots_8_decoded_isSystem;
|
|
reg slots_8_decoded_writesRd;
|
|
reg slots_8_decoded_illegal;
|
|
reg [5:0] slots_8_prs1;
|
|
reg [5:0] slots_8_prs2;
|
|
reg slots_8_src1Ready;
|
|
reg slots_8_src2Ready;
|
|
reg [5:0] slots_8_prd;
|
|
reg [5:0] slots_8_robIdx;
|
|
reg [63:0] slots_9_decoded_pc;
|
|
reg [31:0] slots_9_decoded_inst;
|
|
reg [4:0] slots_9_decoded_rs1;
|
|
reg [4:0] slots_9_decoded_rs2;
|
|
reg [2:0] slots_9_decoded_funct3;
|
|
reg [63:0] slots_9_decoded_immI;
|
|
reg [63:0] slots_9_decoded_immS;
|
|
reg [63:0] slots_9_decoded_immB;
|
|
reg [63:0] slots_9_decoded_immU;
|
|
reg [63:0] slots_9_decoded_immJ;
|
|
reg [4:0] slots_9_decoded_aluFn;
|
|
reg [2:0] slots_9_decoded_memWidth;
|
|
reg slots_9_decoded_isLoad;
|
|
reg slots_9_decoded_isStore;
|
|
reg slots_9_decoded_isBranch;
|
|
reg slots_9_decoded_isJal;
|
|
reg slots_9_decoded_isJalr;
|
|
reg slots_9_decoded_isLui;
|
|
reg slots_9_decoded_isAuipc;
|
|
reg slots_9_decoded_isOpImm;
|
|
reg slots_9_decoded_isWord;
|
|
reg slots_9_decoded_isSystem;
|
|
reg slots_9_decoded_writesRd;
|
|
reg slots_9_decoded_illegal;
|
|
reg [5:0] slots_9_prs1;
|
|
reg [5:0] slots_9_prs2;
|
|
reg slots_9_src1Ready;
|
|
reg slots_9_src2Ready;
|
|
reg [5:0] slots_9_prd;
|
|
reg [5:0] slots_9_robIdx;
|
|
reg [63:0] slots_10_decoded_pc;
|
|
reg [31:0] slots_10_decoded_inst;
|
|
reg [4:0] slots_10_decoded_rs1;
|
|
reg [4:0] slots_10_decoded_rs2;
|
|
reg [2:0] slots_10_decoded_funct3;
|
|
reg [63:0] slots_10_decoded_immI;
|
|
reg [63:0] slots_10_decoded_immS;
|
|
reg [63:0] slots_10_decoded_immB;
|
|
reg [63:0] slots_10_decoded_immU;
|
|
reg [63:0] slots_10_decoded_immJ;
|
|
reg [4:0] slots_10_decoded_aluFn;
|
|
reg [2:0] slots_10_decoded_memWidth;
|
|
reg slots_10_decoded_isLoad;
|
|
reg slots_10_decoded_isStore;
|
|
reg slots_10_decoded_isBranch;
|
|
reg slots_10_decoded_isJal;
|
|
reg slots_10_decoded_isJalr;
|
|
reg slots_10_decoded_isLui;
|
|
reg slots_10_decoded_isAuipc;
|
|
reg slots_10_decoded_isOpImm;
|
|
reg slots_10_decoded_isWord;
|
|
reg slots_10_decoded_isSystem;
|
|
reg slots_10_decoded_writesRd;
|
|
reg slots_10_decoded_illegal;
|
|
reg [5:0] slots_10_prs1;
|
|
reg [5:0] slots_10_prs2;
|
|
reg slots_10_src1Ready;
|
|
reg slots_10_src2Ready;
|
|
reg [5:0] slots_10_prd;
|
|
reg [5:0] slots_10_robIdx;
|
|
reg [63:0] slots_11_decoded_pc;
|
|
reg [31:0] slots_11_decoded_inst;
|
|
reg [4:0] slots_11_decoded_rs1;
|
|
reg [4:0] slots_11_decoded_rs2;
|
|
reg [2:0] slots_11_decoded_funct3;
|
|
reg [63:0] slots_11_decoded_immI;
|
|
reg [63:0] slots_11_decoded_immS;
|
|
reg [63:0] slots_11_decoded_immB;
|
|
reg [63:0] slots_11_decoded_immU;
|
|
reg [63:0] slots_11_decoded_immJ;
|
|
reg [4:0] slots_11_decoded_aluFn;
|
|
reg [2:0] slots_11_decoded_memWidth;
|
|
reg slots_11_decoded_isLoad;
|
|
reg slots_11_decoded_isStore;
|
|
reg slots_11_decoded_isBranch;
|
|
reg slots_11_decoded_isJal;
|
|
reg slots_11_decoded_isJalr;
|
|
reg slots_11_decoded_isLui;
|
|
reg slots_11_decoded_isAuipc;
|
|
reg slots_11_decoded_isOpImm;
|
|
reg slots_11_decoded_isWord;
|
|
reg slots_11_decoded_isSystem;
|
|
reg slots_11_decoded_writesRd;
|
|
reg slots_11_decoded_illegal;
|
|
reg [5:0] slots_11_prs1;
|
|
reg [5:0] slots_11_prs2;
|
|
reg slots_11_src1Ready;
|
|
reg slots_11_src2Ready;
|
|
reg [5:0] slots_11_prd;
|
|
reg [5:0] slots_11_robIdx;
|
|
reg [63:0] slots_12_decoded_pc;
|
|
reg [31:0] slots_12_decoded_inst;
|
|
reg [4:0] slots_12_decoded_rs1;
|
|
reg [4:0] slots_12_decoded_rs2;
|
|
reg [2:0] slots_12_decoded_funct3;
|
|
reg [63:0] slots_12_decoded_immI;
|
|
reg [63:0] slots_12_decoded_immS;
|
|
reg [63:0] slots_12_decoded_immB;
|
|
reg [63:0] slots_12_decoded_immU;
|
|
reg [63:0] slots_12_decoded_immJ;
|
|
reg [4:0] slots_12_decoded_aluFn;
|
|
reg [2:0] slots_12_decoded_memWidth;
|
|
reg slots_12_decoded_isLoad;
|
|
reg slots_12_decoded_isStore;
|
|
reg slots_12_decoded_isBranch;
|
|
reg slots_12_decoded_isJal;
|
|
reg slots_12_decoded_isJalr;
|
|
reg slots_12_decoded_isLui;
|
|
reg slots_12_decoded_isAuipc;
|
|
reg slots_12_decoded_isOpImm;
|
|
reg slots_12_decoded_isWord;
|
|
reg slots_12_decoded_isSystem;
|
|
reg slots_12_decoded_writesRd;
|
|
reg slots_12_decoded_illegal;
|
|
reg [5:0] slots_12_prs1;
|
|
reg [5:0] slots_12_prs2;
|
|
reg slots_12_src1Ready;
|
|
reg slots_12_src2Ready;
|
|
reg [5:0] slots_12_prd;
|
|
reg [5:0] slots_12_robIdx;
|
|
reg [63:0] slots_13_decoded_pc;
|
|
reg [31:0] slots_13_decoded_inst;
|
|
reg [4:0] slots_13_decoded_rs1;
|
|
reg [4:0] slots_13_decoded_rs2;
|
|
reg [2:0] slots_13_decoded_funct3;
|
|
reg [63:0] slots_13_decoded_immI;
|
|
reg [63:0] slots_13_decoded_immS;
|
|
reg [63:0] slots_13_decoded_immB;
|
|
reg [63:0] slots_13_decoded_immU;
|
|
reg [63:0] slots_13_decoded_immJ;
|
|
reg [4:0] slots_13_decoded_aluFn;
|
|
reg [2:0] slots_13_decoded_memWidth;
|
|
reg slots_13_decoded_isLoad;
|
|
reg slots_13_decoded_isStore;
|
|
reg slots_13_decoded_isBranch;
|
|
reg slots_13_decoded_isJal;
|
|
reg slots_13_decoded_isJalr;
|
|
reg slots_13_decoded_isLui;
|
|
reg slots_13_decoded_isAuipc;
|
|
reg slots_13_decoded_isOpImm;
|
|
reg slots_13_decoded_isWord;
|
|
reg slots_13_decoded_isSystem;
|
|
reg slots_13_decoded_writesRd;
|
|
reg slots_13_decoded_illegal;
|
|
reg [5:0] slots_13_prs1;
|
|
reg [5:0] slots_13_prs2;
|
|
reg slots_13_src1Ready;
|
|
reg slots_13_src2Ready;
|
|
reg [5:0] slots_13_prd;
|
|
reg [5:0] slots_13_robIdx;
|
|
reg [63:0] slots_14_decoded_pc;
|
|
reg [31:0] slots_14_decoded_inst;
|
|
reg [4:0] slots_14_decoded_rs1;
|
|
reg [4:0] slots_14_decoded_rs2;
|
|
reg [2:0] slots_14_decoded_funct3;
|
|
reg [63:0] slots_14_decoded_immI;
|
|
reg [63:0] slots_14_decoded_immS;
|
|
reg [63:0] slots_14_decoded_immB;
|
|
reg [63:0] slots_14_decoded_immU;
|
|
reg [63:0] slots_14_decoded_immJ;
|
|
reg [4:0] slots_14_decoded_aluFn;
|
|
reg [2:0] slots_14_decoded_memWidth;
|
|
reg slots_14_decoded_isLoad;
|
|
reg slots_14_decoded_isStore;
|
|
reg slots_14_decoded_isBranch;
|
|
reg slots_14_decoded_isJal;
|
|
reg slots_14_decoded_isJalr;
|
|
reg slots_14_decoded_isLui;
|
|
reg slots_14_decoded_isAuipc;
|
|
reg slots_14_decoded_isOpImm;
|
|
reg slots_14_decoded_isWord;
|
|
reg slots_14_decoded_isSystem;
|
|
reg slots_14_decoded_writesRd;
|
|
reg slots_14_decoded_illegal;
|
|
reg [5:0] slots_14_prs1;
|
|
reg [5:0] slots_14_prs2;
|
|
reg slots_14_src1Ready;
|
|
reg slots_14_src2Ready;
|
|
reg [5:0] slots_14_prd;
|
|
reg [5:0] slots_14_robIdx;
|
|
reg [63:0] slots_15_decoded_pc;
|
|
reg [31:0] slots_15_decoded_inst;
|
|
reg [4:0] slots_15_decoded_rs1;
|
|
reg [4:0] slots_15_decoded_rs2;
|
|
reg [2:0] slots_15_decoded_funct3;
|
|
reg [63:0] slots_15_decoded_immI;
|
|
reg [63:0] slots_15_decoded_immS;
|
|
reg [63:0] slots_15_decoded_immB;
|
|
reg [63:0] slots_15_decoded_immU;
|
|
reg [63:0] slots_15_decoded_immJ;
|
|
reg [4:0] slots_15_decoded_aluFn;
|
|
reg [2:0] slots_15_decoded_memWidth;
|
|
reg slots_15_decoded_isLoad;
|
|
reg slots_15_decoded_isStore;
|
|
reg slots_15_decoded_isBranch;
|
|
reg slots_15_decoded_isJal;
|
|
reg slots_15_decoded_isJalr;
|
|
reg slots_15_decoded_isLui;
|
|
reg slots_15_decoded_isAuipc;
|
|
reg slots_15_decoded_isOpImm;
|
|
reg slots_15_decoded_isWord;
|
|
reg slots_15_decoded_isSystem;
|
|
reg slots_15_decoded_writesRd;
|
|
reg slots_15_decoded_illegal;
|
|
reg [5:0] slots_15_prs1;
|
|
reg [5:0] slots_15_prs2;
|
|
reg slots_15_src1Ready;
|
|
reg slots_15_src2Ready;
|
|
reg [5:0] slots_15_prd;
|
|
reg [5:0] slots_15_robIdx;
|
|
wire [15:0] freeMask =
|
|
{~valid_15,
|
|
~valid_14,
|
|
~valid_13,
|
|
~valid_12,
|
|
~valid_11,
|
|
~valid_10,
|
|
~valid_9,
|
|
~valid_8,
|
|
~valid_7,
|
|
~valid_6,
|
|
~valid_5,
|
|
~valid_4,
|
|
~valid_3,
|
|
~valid_2,
|
|
~valid_1,
|
|
~valid_0};
|
|
wire [15:0] enq0OH =
|
|
valid_0
|
|
? (valid_1
|
|
? (valid_2
|
|
? (valid_3
|
|
? (valid_4
|
|
? (valid_5
|
|
? (valid_6
|
|
? (valid_7
|
|
? (valid_8
|
|
? (valid_9
|
|
? (valid_10
|
|
? (valid_11
|
|
? (valid_12
|
|
? (valid_13
|
|
? (valid_14
|
|
? {~valid_15,
|
|
15'h0}
|
|
: 16'h4000)
|
|
: 16'h2000)
|
|
: 16'h1000)
|
|
: 16'h800)
|
|
: 16'h400)
|
|
: 16'h200)
|
|
: 16'h100)
|
|
: 16'h80)
|
|
: 16'h40)
|
|
: 16'h20)
|
|
: 16'h10)
|
|
: 16'h8)
|
|
: 16'h4)
|
|
: 16'h2)
|
|
: 16'h1;
|
|
wire [15:0] _io_enqReady_1_T = ~enq0OH;
|
|
wire [15:0] _io_enqReady_1_T_1 = freeMask & _io_enqReady_1_T;
|
|
wire _src1Wake_T = io_wakeup_0_phys == slots_0_prs1;
|
|
wire _src1Wake_T_2 = io_wakeup_1_phys == slots_0_prs1;
|
|
wire _src2Wake_T = io_wakeup_0_phys == slots_0_prs2;
|
|
wire _src2Wake_T_2 = io_wakeup_1_phys == slots_0_prs2;
|
|
wire readyVec_0 =
|
|
valid_0
|
|
& (slots_0_src1Ready | io_wakeup_0_valid & _src1Wake_T | io_wakeup_1_valid
|
|
& _src1Wake_T_2 | slots_0_decoded_rs1 == 5'h0)
|
|
& (slots_0_src2Ready | io_wakeup_0_valid & _src2Wake_T | io_wakeup_1_valid
|
|
& _src2Wake_T_2 | slots_0_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_4 = io_wakeup_0_phys == slots_1_prs1;
|
|
wire _src1Wake_T_6 = io_wakeup_1_phys == slots_1_prs1;
|
|
wire _src2Wake_T_4 = io_wakeup_0_phys == slots_1_prs2;
|
|
wire _src2Wake_T_6 = io_wakeup_1_phys == slots_1_prs2;
|
|
wire readyVec_1 =
|
|
valid_1
|
|
& (slots_1_src1Ready | io_wakeup_0_valid & _src1Wake_T_4 | io_wakeup_1_valid
|
|
& _src1Wake_T_6 | slots_1_decoded_rs1 == 5'h0)
|
|
& (slots_1_src2Ready | io_wakeup_0_valid & _src2Wake_T_4 | io_wakeup_1_valid
|
|
& _src2Wake_T_6 | slots_1_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_8 = io_wakeup_0_phys == slots_2_prs1;
|
|
wire _src1Wake_T_10 = io_wakeup_1_phys == slots_2_prs1;
|
|
wire _src2Wake_T_8 = io_wakeup_0_phys == slots_2_prs2;
|
|
wire _src2Wake_T_10 = io_wakeup_1_phys == slots_2_prs2;
|
|
wire readyVec_2 =
|
|
valid_2
|
|
& (slots_2_src1Ready | io_wakeup_0_valid & _src1Wake_T_8 | io_wakeup_1_valid
|
|
& _src1Wake_T_10 | slots_2_decoded_rs1 == 5'h0)
|
|
& (slots_2_src2Ready | io_wakeup_0_valid & _src2Wake_T_8 | io_wakeup_1_valid
|
|
& _src2Wake_T_10 | slots_2_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_12 = io_wakeup_0_phys == slots_3_prs1;
|
|
wire _src1Wake_T_14 = io_wakeup_1_phys == slots_3_prs1;
|
|
wire _src2Wake_T_12 = io_wakeup_0_phys == slots_3_prs2;
|
|
wire _src2Wake_T_14 = io_wakeup_1_phys == slots_3_prs2;
|
|
wire readyVec_3 =
|
|
valid_3
|
|
& (slots_3_src1Ready | io_wakeup_0_valid & _src1Wake_T_12 | io_wakeup_1_valid
|
|
& _src1Wake_T_14 | slots_3_decoded_rs1 == 5'h0)
|
|
& (slots_3_src2Ready | io_wakeup_0_valid & _src2Wake_T_12 | io_wakeup_1_valid
|
|
& _src2Wake_T_14 | slots_3_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_16 = io_wakeup_0_phys == slots_4_prs1;
|
|
wire _src1Wake_T_18 = io_wakeup_1_phys == slots_4_prs1;
|
|
wire _src2Wake_T_16 = io_wakeup_0_phys == slots_4_prs2;
|
|
wire _src2Wake_T_18 = io_wakeup_1_phys == slots_4_prs2;
|
|
wire readyVec_4 =
|
|
valid_4
|
|
& (slots_4_src1Ready | io_wakeup_0_valid & _src1Wake_T_16 | io_wakeup_1_valid
|
|
& _src1Wake_T_18 | slots_4_decoded_rs1 == 5'h0)
|
|
& (slots_4_src2Ready | io_wakeup_0_valid & _src2Wake_T_16 | io_wakeup_1_valid
|
|
& _src2Wake_T_18 | slots_4_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_20 = io_wakeup_0_phys == slots_5_prs1;
|
|
wire _src1Wake_T_22 = io_wakeup_1_phys == slots_5_prs1;
|
|
wire _src2Wake_T_20 = io_wakeup_0_phys == slots_5_prs2;
|
|
wire _src2Wake_T_22 = io_wakeup_1_phys == slots_5_prs2;
|
|
wire readyVec_5 =
|
|
valid_5
|
|
& (slots_5_src1Ready | io_wakeup_0_valid & _src1Wake_T_20 | io_wakeup_1_valid
|
|
& _src1Wake_T_22 | slots_5_decoded_rs1 == 5'h0)
|
|
& (slots_5_src2Ready | io_wakeup_0_valid & _src2Wake_T_20 | io_wakeup_1_valid
|
|
& _src2Wake_T_22 | slots_5_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_24 = io_wakeup_0_phys == slots_6_prs1;
|
|
wire _src1Wake_T_26 = io_wakeup_1_phys == slots_6_prs1;
|
|
wire _src2Wake_T_24 = io_wakeup_0_phys == slots_6_prs2;
|
|
wire _src2Wake_T_26 = io_wakeup_1_phys == slots_6_prs2;
|
|
wire readyVec_6 =
|
|
valid_6
|
|
& (slots_6_src1Ready | io_wakeup_0_valid & _src1Wake_T_24 | io_wakeup_1_valid
|
|
& _src1Wake_T_26 | slots_6_decoded_rs1 == 5'h0)
|
|
& (slots_6_src2Ready | io_wakeup_0_valid & _src2Wake_T_24 | io_wakeup_1_valid
|
|
& _src2Wake_T_26 | slots_6_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_28 = io_wakeup_0_phys == slots_7_prs1;
|
|
wire _src1Wake_T_30 = io_wakeup_1_phys == slots_7_prs1;
|
|
wire _src2Wake_T_28 = io_wakeup_0_phys == slots_7_prs2;
|
|
wire _src2Wake_T_30 = io_wakeup_1_phys == slots_7_prs2;
|
|
wire readyVec_7 =
|
|
valid_7
|
|
& (slots_7_src1Ready | io_wakeup_0_valid & _src1Wake_T_28 | io_wakeup_1_valid
|
|
& _src1Wake_T_30 | slots_7_decoded_rs1 == 5'h0)
|
|
& (slots_7_src2Ready | io_wakeup_0_valid & _src2Wake_T_28 | io_wakeup_1_valid
|
|
& _src2Wake_T_30 | slots_7_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_32 = io_wakeup_0_phys == slots_8_prs1;
|
|
wire _src1Wake_T_34 = io_wakeup_1_phys == slots_8_prs1;
|
|
wire _src2Wake_T_32 = io_wakeup_0_phys == slots_8_prs2;
|
|
wire _src2Wake_T_34 = io_wakeup_1_phys == slots_8_prs2;
|
|
wire readyVec_8 =
|
|
valid_8
|
|
& (slots_8_src1Ready | io_wakeup_0_valid & _src1Wake_T_32 | io_wakeup_1_valid
|
|
& _src1Wake_T_34 | slots_8_decoded_rs1 == 5'h0)
|
|
& (slots_8_src2Ready | io_wakeup_0_valid & _src2Wake_T_32 | io_wakeup_1_valid
|
|
& _src2Wake_T_34 | slots_8_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_36 = io_wakeup_0_phys == slots_9_prs1;
|
|
wire _src1Wake_T_38 = io_wakeup_1_phys == slots_9_prs1;
|
|
wire _src2Wake_T_36 = io_wakeup_0_phys == slots_9_prs2;
|
|
wire _src2Wake_T_38 = io_wakeup_1_phys == slots_9_prs2;
|
|
wire readyVec_9 =
|
|
valid_9
|
|
& (slots_9_src1Ready | io_wakeup_0_valid & _src1Wake_T_36 | io_wakeup_1_valid
|
|
& _src1Wake_T_38 | slots_9_decoded_rs1 == 5'h0)
|
|
& (slots_9_src2Ready | io_wakeup_0_valid & _src2Wake_T_36 | io_wakeup_1_valid
|
|
& _src2Wake_T_38 | slots_9_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_40 = io_wakeup_0_phys == slots_10_prs1;
|
|
wire _src1Wake_T_42 = io_wakeup_1_phys == slots_10_prs1;
|
|
wire _src2Wake_T_40 = io_wakeup_0_phys == slots_10_prs2;
|
|
wire _src2Wake_T_42 = io_wakeup_1_phys == slots_10_prs2;
|
|
wire readyVec_10 =
|
|
valid_10
|
|
& (slots_10_src1Ready | io_wakeup_0_valid & _src1Wake_T_40 | io_wakeup_1_valid
|
|
& _src1Wake_T_42 | slots_10_decoded_rs1 == 5'h0)
|
|
& (slots_10_src2Ready | io_wakeup_0_valid & _src2Wake_T_40 | io_wakeup_1_valid
|
|
& _src2Wake_T_42 | slots_10_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_44 = io_wakeup_0_phys == slots_11_prs1;
|
|
wire _src1Wake_T_46 = io_wakeup_1_phys == slots_11_prs1;
|
|
wire _src2Wake_T_44 = io_wakeup_0_phys == slots_11_prs2;
|
|
wire _src2Wake_T_46 = io_wakeup_1_phys == slots_11_prs2;
|
|
wire readyVec_11 =
|
|
valid_11
|
|
& (slots_11_src1Ready | io_wakeup_0_valid & _src1Wake_T_44 | io_wakeup_1_valid
|
|
& _src1Wake_T_46 | slots_11_decoded_rs1 == 5'h0)
|
|
& (slots_11_src2Ready | io_wakeup_0_valid & _src2Wake_T_44 | io_wakeup_1_valid
|
|
& _src2Wake_T_46 | slots_11_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_48 = io_wakeup_0_phys == slots_12_prs1;
|
|
wire _src1Wake_T_50 = io_wakeup_1_phys == slots_12_prs1;
|
|
wire _src2Wake_T_48 = io_wakeup_0_phys == slots_12_prs2;
|
|
wire _src2Wake_T_50 = io_wakeup_1_phys == slots_12_prs2;
|
|
wire readyVec_12 =
|
|
valid_12
|
|
& (slots_12_src1Ready | io_wakeup_0_valid & _src1Wake_T_48 | io_wakeup_1_valid
|
|
& _src1Wake_T_50 | slots_12_decoded_rs1 == 5'h0)
|
|
& (slots_12_src2Ready | io_wakeup_0_valid & _src2Wake_T_48 | io_wakeup_1_valid
|
|
& _src2Wake_T_50 | slots_12_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_52 = io_wakeup_0_phys == slots_13_prs1;
|
|
wire _src1Wake_T_54 = io_wakeup_1_phys == slots_13_prs1;
|
|
wire _src2Wake_T_52 = io_wakeup_0_phys == slots_13_prs2;
|
|
wire _src2Wake_T_54 = io_wakeup_1_phys == slots_13_prs2;
|
|
wire readyVec_13 =
|
|
valid_13
|
|
& (slots_13_src1Ready | io_wakeup_0_valid & _src1Wake_T_52 | io_wakeup_1_valid
|
|
& _src1Wake_T_54 | slots_13_decoded_rs1 == 5'h0)
|
|
& (slots_13_src2Ready | io_wakeup_0_valid & _src2Wake_T_52 | io_wakeup_1_valid
|
|
& _src2Wake_T_54 | slots_13_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_56 = io_wakeup_0_phys == slots_14_prs1;
|
|
wire _src1Wake_T_58 = io_wakeup_1_phys == slots_14_prs1;
|
|
wire _src2Wake_T_56 = io_wakeup_0_phys == slots_14_prs2;
|
|
wire _src2Wake_T_58 = io_wakeup_1_phys == slots_14_prs2;
|
|
wire readyVec_14 =
|
|
valid_14
|
|
& (slots_14_src1Ready | io_wakeup_0_valid & _src1Wake_T_56 | io_wakeup_1_valid
|
|
& _src1Wake_T_58 | slots_14_decoded_rs1 == 5'h0)
|
|
& (slots_14_src2Ready | io_wakeup_0_valid & _src2Wake_T_56 | io_wakeup_1_valid
|
|
& _src2Wake_T_58 | slots_14_decoded_rs2 == 5'h0);
|
|
wire _src1Wake_T_60 = io_wakeup_0_phys == slots_15_prs1;
|
|
wire _src1Wake_T_62 = io_wakeup_1_phys == slots_15_prs1;
|
|
wire _src2Wake_T_60 = io_wakeup_0_phys == slots_15_prs2;
|
|
wire _src2Wake_T_62 = io_wakeup_1_phys == slots_15_prs2;
|
|
wire readyVec_15 =
|
|
valid_15
|
|
& (slots_15_src1Ready | io_wakeup_0_valid & _src1Wake_T_60 | io_wakeup_1_valid
|
|
& _src1Wake_T_62 | slots_15_decoded_rs1 == 5'h0)
|
|
& (slots_15_src2Ready | io_wakeup_0_valid & _src2Wake_T_60 | io_wakeup_1_valid
|
|
& _src2Wake_T_62 | slots_15_decoded_rs2 == 5'h0);
|
|
wire [15:0] _io_issueValid_1_T =
|
|
{readyVec_15,
|
|
readyVec_14,
|
|
readyVec_13,
|
|
readyVec_12,
|
|
readyVec_11,
|
|
readyVec_10,
|
|
readyVec_9,
|
|
readyVec_8,
|
|
readyVec_7,
|
|
readyVec_6,
|
|
readyVec_5,
|
|
readyVec_4,
|
|
readyVec_3,
|
|
readyVec_2,
|
|
readyVec_1,
|
|
readyVec_0};
|
|
wire [15:0] issue0OH =
|
|
readyVec_0
|
|
? 16'h1
|
|
: readyVec_1
|
|
? 16'h2
|
|
: readyVec_2
|
|
? 16'h4
|
|
: readyVec_3
|
|
? 16'h8
|
|
: readyVec_4
|
|
? 16'h10
|
|
: readyVec_5
|
|
? 16'h20
|
|
: readyVec_6
|
|
? 16'h40
|
|
: readyVec_7
|
|
? 16'h80
|
|
: readyVec_8
|
|
? 16'h100
|
|
: readyVec_9
|
|
? 16'h200
|
|
: readyVec_10
|
|
? 16'h400
|
|
: readyVec_11
|
|
? 16'h800
|
|
: readyVec_12
|
|
? 16'h1000
|
|
: readyVec_13
|
|
? 16'h2000
|
|
: readyVec_14
|
|
? 16'h4000
|
|
: {readyVec_15, 15'h0};
|
|
wire [15:0] _io_issueValid_1_T_1 = ~issue0OH;
|
|
wire [15:0] issue1OH =
|
|
readyVec_0 & _io_issueValid_1_T_1[0]
|
|
? 16'h1
|
|
: readyVec_1 & _io_issueValid_1_T_1[1]
|
|
? 16'h2
|
|
: readyVec_2 & _io_issueValid_1_T_1[2]
|
|
? 16'h4
|
|
: readyVec_3 & _io_issueValid_1_T_1[3]
|
|
? 16'h8
|
|
: readyVec_4 & _io_issueValid_1_T_1[4]
|
|
? 16'h10
|
|
: readyVec_5 & _io_issueValid_1_T_1[5]
|
|
? 16'h20
|
|
: readyVec_6 & _io_issueValid_1_T_1[6]
|
|
? 16'h40
|
|
: readyVec_7 & _io_issueValid_1_T_1[7]
|
|
? 16'h80
|
|
: readyVec_8 & _io_issueValid_1_T_1[8]
|
|
? 16'h100
|
|
: readyVec_9 & _io_issueValid_1_T_1[9]
|
|
? 16'h200
|
|
: readyVec_10 & _io_issueValid_1_T_1[10]
|
|
? 16'h400
|
|
: readyVec_11 & _io_issueValid_1_T_1[11]
|
|
? 16'h800
|
|
: readyVec_12 & _io_issueValid_1_T_1[12]
|
|
? 16'h1000
|
|
: readyVec_13
|
|
& _io_issueValid_1_T_1[13]
|
|
? 16'h2000
|
|
: readyVec_14
|
|
& _io_issueValid_1_T_1[14]
|
|
? 16'h4000
|
|
: {readyVec_15
|
|
& _io_issueValid_1_T_1[15],
|
|
15'h0};
|
|
always @(posedge clock) begin
|
|
automatic logic [15:0] enq1OH =
|
|
~valid_0 & _io_enqReady_1_T[0]
|
|
? 16'h1
|
|
: ~valid_1 & _io_enqReady_1_T[1]
|
|
? 16'h2
|
|
: ~valid_2 & _io_enqReady_1_T[2]
|
|
? 16'h4
|
|
: ~valid_3 & _io_enqReady_1_T[3]
|
|
? 16'h8
|
|
: ~valid_4 & _io_enqReady_1_T[4]
|
|
? 16'h10
|
|
: ~valid_5 & _io_enqReady_1_T[5]
|
|
? 16'h20
|
|
: ~valid_6 & _io_enqReady_1_T[6]
|
|
? 16'h40
|
|
: ~valid_7 & _io_enqReady_1_T[7]
|
|
? 16'h80
|
|
: ~valid_8 & _io_enqReady_1_T[8]
|
|
? 16'h100
|
|
: ~valid_9 & _io_enqReady_1_T[9]
|
|
? 16'h200
|
|
: ~valid_10 & _io_enqReady_1_T[10]
|
|
? 16'h400
|
|
: ~valid_11 & _io_enqReady_1_T[11]
|
|
? 16'h800
|
|
: ~valid_12 & _io_enqReady_1_T[12]
|
|
? 16'h1000
|
|
: ~valid_13 & _io_enqReady_1_T[13]
|
|
? 16'h2000
|
|
: ~valid_14
|
|
& _io_enqReady_1_T[14]
|
|
? 16'h4000
|
|
: {~valid_15
|
|
& _io_enqReady_1_T[15],
|
|
15'h0};
|
|
automatic logic _GEN;
|
|
automatic logic _GEN_0;
|
|
automatic logic _GEN_1;
|
|
automatic logic _GEN_2;
|
|
automatic logic _GEN_3;
|
|
automatic logic _GEN_4;
|
|
automatic logic _GEN_5;
|
|
automatic logic _GEN_6;
|
|
automatic logic _GEN_7;
|
|
automatic logic _GEN_8;
|
|
automatic logic _GEN_9;
|
|
automatic logic _GEN_10;
|
|
automatic logic _GEN_11;
|
|
automatic logic _GEN_12;
|
|
automatic logic _GEN_13;
|
|
automatic logic _GEN_14;
|
|
automatic logic _GEN_15;
|
|
automatic logic _GEN_16;
|
|
automatic logic _GEN_17;
|
|
automatic logic _GEN_18;
|
|
automatic logic _GEN_19;
|
|
automatic logic _GEN_20;
|
|
automatic logic _GEN_21;
|
|
automatic logic _GEN_22;
|
|
automatic logic _GEN_23;
|
|
automatic logic _GEN_24;
|
|
automatic logic _GEN_25;
|
|
automatic logic _GEN_26;
|
|
automatic logic _GEN_27;
|
|
automatic logic _GEN_28;
|
|
automatic logic _GEN_29;
|
|
automatic logic _GEN_30;
|
|
_GEN = enq0OH[0] & io_enqValid_0 & (|freeMask);
|
|
_GEN_0 = enq1OH[0] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_1 = enq0OH[1] & io_enqValid_0 & (|freeMask);
|
|
_GEN_2 = enq1OH[1] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_3 = enq0OH[2] & io_enqValid_0 & (|freeMask);
|
|
_GEN_4 = enq1OH[2] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_5 = enq0OH[3] & io_enqValid_0 & (|freeMask);
|
|
_GEN_6 = enq1OH[3] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_7 = enq0OH[4] & io_enqValid_0 & (|freeMask);
|
|
_GEN_8 = enq1OH[4] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_9 = enq0OH[5] & io_enqValid_0 & (|freeMask);
|
|
_GEN_10 = enq1OH[5] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_11 = enq0OH[6] & io_enqValid_0 & (|freeMask);
|
|
_GEN_12 = enq1OH[6] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_13 = enq0OH[7] & io_enqValid_0 & (|freeMask);
|
|
_GEN_14 = enq1OH[7] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_15 = enq0OH[8] & io_enqValid_0 & (|freeMask);
|
|
_GEN_16 = enq1OH[8] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_17 = enq0OH[9] & io_enqValid_0 & (|freeMask);
|
|
_GEN_18 = enq1OH[9] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_19 = enq0OH[10] & io_enqValid_0 & (|freeMask);
|
|
_GEN_20 = enq1OH[10] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_21 = enq0OH[11] & io_enqValid_0 & (|freeMask);
|
|
_GEN_22 = enq1OH[11] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_23 = enq0OH[12] & io_enqValid_0 & (|freeMask);
|
|
_GEN_24 = enq1OH[12] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_25 = enq0OH[13] & io_enqValid_0 & (|freeMask);
|
|
_GEN_26 = enq1OH[13] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_27 = enq0OH[14] & io_enqValid_0 & (|freeMask);
|
|
_GEN_28 = enq1OH[14] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
_GEN_29 = enq0OH[15] & io_enqValid_0 & (|freeMask);
|
|
_GEN_30 = enq1OH[15] & io_enqValid_1 & (|_io_enqReady_1_T_1);
|
|
if (reset) begin
|
|
valid_0 <= 1'h0;
|
|
valid_1 <= 1'h0;
|
|
valid_2 <= 1'h0;
|
|
valid_3 <= 1'h0;
|
|
valid_4 <= 1'h0;
|
|
valid_5 <= 1'h0;
|
|
valid_6 <= 1'h0;
|
|
valid_7 <= 1'h0;
|
|
valid_8 <= 1'h0;
|
|
valid_9 <= 1'h0;
|
|
valid_10 <= 1'h0;
|
|
valid_11 <= 1'h0;
|
|
valid_12 <= 1'h0;
|
|
valid_13 <= 1'h0;
|
|
valid_14 <= 1'h0;
|
|
valid_15 <= 1'h0;
|
|
end
|
|
else begin
|
|
valid_0 <=
|
|
~io_flush
|
|
& (_GEN_0 | _GEN
|
|
| ~(issue1OH[0] & io_issueReady_1 | issue0OH[0] & io_issueReady_0) & valid_0);
|
|
valid_1 <=
|
|
~io_flush
|
|
& (_GEN_2 | _GEN_1
|
|
| ~(issue1OH[1] & io_issueReady_1 | issue0OH[1] & io_issueReady_0) & valid_1);
|
|
valid_2 <=
|
|
~io_flush
|
|
& (_GEN_4 | _GEN_3
|
|
| ~(issue1OH[2] & io_issueReady_1 | issue0OH[2] & io_issueReady_0) & valid_2);
|
|
valid_3 <=
|
|
~io_flush
|
|
& (_GEN_6 | _GEN_5
|
|
| ~(issue1OH[3] & io_issueReady_1 | issue0OH[3] & io_issueReady_0) & valid_3);
|
|
valid_4 <=
|
|
~io_flush
|
|
& (_GEN_8 | _GEN_7
|
|
| ~(issue1OH[4] & io_issueReady_1 | issue0OH[4] & io_issueReady_0) & valid_4);
|
|
valid_5 <=
|
|
~io_flush
|
|
& (_GEN_10 | _GEN_9
|
|
| ~(issue1OH[5] & io_issueReady_1 | issue0OH[5] & io_issueReady_0) & valid_5);
|
|
valid_6 <=
|
|
~io_flush
|
|
& (_GEN_12 | _GEN_11
|
|
| ~(issue1OH[6] & io_issueReady_1 | issue0OH[6] & io_issueReady_0) & valid_6);
|
|
valid_7 <=
|
|
~io_flush
|
|
& (_GEN_14 | _GEN_13
|
|
| ~(issue1OH[7] & io_issueReady_1 | issue0OH[7] & io_issueReady_0) & valid_7);
|
|
valid_8 <=
|
|
~io_flush
|
|
& (_GEN_16 | _GEN_15
|
|
| ~(issue1OH[8] & io_issueReady_1 | issue0OH[8] & io_issueReady_0) & valid_8);
|
|
valid_9 <=
|
|
~io_flush
|
|
& (_GEN_18 | _GEN_17
|
|
| ~(issue1OH[9] & io_issueReady_1 | issue0OH[9] & io_issueReady_0) & valid_9);
|
|
valid_10 <=
|
|
~io_flush
|
|
& (_GEN_20 | _GEN_19
|
|
| ~(issue1OH[10] & io_issueReady_1 | issue0OH[10] & io_issueReady_0)
|
|
& valid_10);
|
|
valid_11 <=
|
|
~io_flush
|
|
& (_GEN_22 | _GEN_21
|
|
| ~(issue1OH[11] & io_issueReady_1 | issue0OH[11] & io_issueReady_0)
|
|
& valid_11);
|
|
valid_12 <=
|
|
~io_flush
|
|
& (_GEN_24 | _GEN_23
|
|
| ~(issue1OH[12] & io_issueReady_1 | issue0OH[12] & io_issueReady_0)
|
|
& valid_12);
|
|
valid_13 <=
|
|
~io_flush
|
|
& (_GEN_26 | _GEN_25
|
|
| ~(issue1OH[13] & io_issueReady_1 | issue0OH[13] & io_issueReady_0)
|
|
& valid_13);
|
|
valid_14 <=
|
|
~io_flush
|
|
& (_GEN_28 | _GEN_27
|
|
| ~(issue1OH[14] & io_issueReady_1 | issue0OH[14] & io_issueReady_0)
|
|
& valid_14);
|
|
valid_15 <=
|
|
~io_flush
|
|
& (_GEN_30 | _GEN_29
|
|
| ~(issue1OH[15] & io_issueReady_1 | issue0OH[15] & io_issueReady_0)
|
|
& valid_15);
|
|
end
|
|
if (io_flush) begin
|
|
end
|
|
else begin
|
|
if (_GEN_0) begin
|
|
slots_0_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_0_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_0_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_0_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_0_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_0_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_0_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_0_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_0_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_0_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_0_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_0_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_0_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_0_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_0_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_0_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_0_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_0_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_0_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_0_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_0_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_0_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_0_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_0_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_0_prs1 <= io_enq_1_prs1;
|
|
slots_0_prs2 <= io_enq_1_prs2;
|
|
slots_0_prd <= io_enq_1_prd;
|
|
slots_0_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN) begin
|
|
slots_0_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_0_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_0_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_0_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_0_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_0_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_0_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_0_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_0_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_0_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_0_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_0_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_0_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_0_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_0_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_0_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_0_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_0_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_0_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_0_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_0_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_0_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_0_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_0_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_0_prs1 <= io_enq_0_prs1;
|
|
slots_0_prs2 <= io_enq_0_prs2;
|
|
slots_0_prd <= io_enq_0_prd;
|
|
slots_0_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_0_src1Ready <=
|
|
_GEN_0
|
|
? io_enq_1_src1Ready
|
|
: _GEN
|
|
? io_enq_0_src1Ready
|
|
: valid_0
|
|
& (io_wakeup_1_valid & _src1Wake_T_2 | io_wakeup_0_valid & _src1Wake_T)
|
|
| slots_0_src1Ready;
|
|
slots_0_src2Ready <=
|
|
_GEN_0
|
|
? io_enq_1_src2Ready
|
|
: _GEN
|
|
? io_enq_0_src2Ready
|
|
: valid_0
|
|
& (io_wakeup_1_valid & _src2Wake_T_2 | io_wakeup_0_valid & _src2Wake_T)
|
|
| slots_0_src2Ready;
|
|
if (_GEN_2) begin
|
|
slots_1_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_1_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_1_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_1_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_1_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_1_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_1_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_1_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_1_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_1_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_1_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_1_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_1_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_1_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_1_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_1_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_1_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_1_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_1_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_1_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_1_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_1_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_1_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_1_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_1_prs1 <= io_enq_1_prs1;
|
|
slots_1_prs2 <= io_enq_1_prs2;
|
|
slots_1_prd <= io_enq_1_prd;
|
|
slots_1_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_1) begin
|
|
slots_1_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_1_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_1_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_1_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_1_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_1_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_1_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_1_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_1_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_1_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_1_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_1_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_1_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_1_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_1_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_1_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_1_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_1_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_1_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_1_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_1_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_1_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_1_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_1_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_1_prs1 <= io_enq_0_prs1;
|
|
slots_1_prs2 <= io_enq_0_prs2;
|
|
slots_1_prd <= io_enq_0_prd;
|
|
slots_1_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_1_src1Ready <=
|
|
_GEN_2
|
|
? io_enq_1_src1Ready
|
|
: _GEN_1
|
|
? io_enq_0_src1Ready
|
|
: valid_1
|
|
& (io_wakeup_1_valid & _src1Wake_T_6 | io_wakeup_0_valid & _src1Wake_T_4)
|
|
| slots_1_src1Ready;
|
|
slots_1_src2Ready <=
|
|
_GEN_2
|
|
? io_enq_1_src2Ready
|
|
: _GEN_1
|
|
? io_enq_0_src2Ready
|
|
: valid_1
|
|
& (io_wakeup_1_valid & _src2Wake_T_6 | io_wakeup_0_valid & _src2Wake_T_4)
|
|
| slots_1_src2Ready;
|
|
if (_GEN_4) begin
|
|
slots_2_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_2_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_2_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_2_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_2_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_2_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_2_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_2_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_2_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_2_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_2_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_2_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_2_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_2_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_2_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_2_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_2_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_2_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_2_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_2_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_2_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_2_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_2_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_2_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_2_prs1 <= io_enq_1_prs1;
|
|
slots_2_prs2 <= io_enq_1_prs2;
|
|
slots_2_prd <= io_enq_1_prd;
|
|
slots_2_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_3) begin
|
|
slots_2_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_2_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_2_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_2_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_2_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_2_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_2_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_2_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_2_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_2_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_2_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_2_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_2_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_2_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_2_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_2_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_2_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_2_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_2_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_2_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_2_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_2_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_2_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_2_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_2_prs1 <= io_enq_0_prs1;
|
|
slots_2_prs2 <= io_enq_0_prs2;
|
|
slots_2_prd <= io_enq_0_prd;
|
|
slots_2_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_2_src1Ready <=
|
|
_GEN_4
|
|
? io_enq_1_src1Ready
|
|
: _GEN_3
|
|
? io_enq_0_src1Ready
|
|
: valid_2
|
|
& (io_wakeup_1_valid & _src1Wake_T_10 | io_wakeup_0_valid & _src1Wake_T_8)
|
|
| slots_2_src1Ready;
|
|
slots_2_src2Ready <=
|
|
_GEN_4
|
|
? io_enq_1_src2Ready
|
|
: _GEN_3
|
|
? io_enq_0_src2Ready
|
|
: valid_2
|
|
& (io_wakeup_1_valid & _src2Wake_T_10 | io_wakeup_0_valid & _src2Wake_T_8)
|
|
| slots_2_src2Ready;
|
|
if (_GEN_6) begin
|
|
slots_3_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_3_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_3_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_3_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_3_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_3_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_3_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_3_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_3_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_3_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_3_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_3_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_3_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_3_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_3_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_3_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_3_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_3_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_3_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_3_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_3_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_3_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_3_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_3_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_3_prs1 <= io_enq_1_prs1;
|
|
slots_3_prs2 <= io_enq_1_prs2;
|
|
slots_3_prd <= io_enq_1_prd;
|
|
slots_3_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_5) begin
|
|
slots_3_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_3_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_3_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_3_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_3_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_3_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_3_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_3_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_3_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_3_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_3_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_3_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_3_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_3_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_3_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_3_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_3_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_3_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_3_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_3_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_3_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_3_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_3_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_3_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_3_prs1 <= io_enq_0_prs1;
|
|
slots_3_prs2 <= io_enq_0_prs2;
|
|
slots_3_prd <= io_enq_0_prd;
|
|
slots_3_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_3_src1Ready <=
|
|
_GEN_6
|
|
? io_enq_1_src1Ready
|
|
: _GEN_5
|
|
? io_enq_0_src1Ready
|
|
: valid_3
|
|
& (io_wakeup_1_valid & _src1Wake_T_14 | io_wakeup_0_valid
|
|
& _src1Wake_T_12) | slots_3_src1Ready;
|
|
slots_3_src2Ready <=
|
|
_GEN_6
|
|
? io_enq_1_src2Ready
|
|
: _GEN_5
|
|
? io_enq_0_src2Ready
|
|
: valid_3
|
|
& (io_wakeup_1_valid & _src2Wake_T_14 | io_wakeup_0_valid
|
|
& _src2Wake_T_12) | slots_3_src2Ready;
|
|
if (_GEN_8) begin
|
|
slots_4_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_4_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_4_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_4_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_4_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_4_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_4_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_4_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_4_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_4_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_4_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_4_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_4_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_4_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_4_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_4_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_4_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_4_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_4_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_4_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_4_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_4_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_4_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_4_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_4_prs1 <= io_enq_1_prs1;
|
|
slots_4_prs2 <= io_enq_1_prs2;
|
|
slots_4_prd <= io_enq_1_prd;
|
|
slots_4_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_7) begin
|
|
slots_4_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_4_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_4_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_4_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_4_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_4_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_4_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_4_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_4_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_4_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_4_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_4_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_4_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_4_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_4_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_4_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_4_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_4_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_4_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_4_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_4_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_4_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_4_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_4_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_4_prs1 <= io_enq_0_prs1;
|
|
slots_4_prs2 <= io_enq_0_prs2;
|
|
slots_4_prd <= io_enq_0_prd;
|
|
slots_4_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_4_src1Ready <=
|
|
_GEN_8
|
|
? io_enq_1_src1Ready
|
|
: _GEN_7
|
|
? io_enq_0_src1Ready
|
|
: valid_4
|
|
& (io_wakeup_1_valid & _src1Wake_T_18 | io_wakeup_0_valid
|
|
& _src1Wake_T_16) | slots_4_src1Ready;
|
|
slots_4_src2Ready <=
|
|
_GEN_8
|
|
? io_enq_1_src2Ready
|
|
: _GEN_7
|
|
? io_enq_0_src2Ready
|
|
: valid_4
|
|
& (io_wakeup_1_valid & _src2Wake_T_18 | io_wakeup_0_valid
|
|
& _src2Wake_T_16) | slots_4_src2Ready;
|
|
if (_GEN_10) begin
|
|
slots_5_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_5_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_5_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_5_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_5_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_5_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_5_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_5_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_5_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_5_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_5_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_5_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_5_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_5_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_5_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_5_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_5_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_5_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_5_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_5_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_5_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_5_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_5_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_5_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_5_prs1 <= io_enq_1_prs1;
|
|
slots_5_prs2 <= io_enq_1_prs2;
|
|
slots_5_prd <= io_enq_1_prd;
|
|
slots_5_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_9) begin
|
|
slots_5_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_5_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_5_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_5_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_5_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_5_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_5_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_5_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_5_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_5_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_5_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_5_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_5_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_5_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_5_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_5_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_5_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_5_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_5_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_5_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_5_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_5_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_5_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_5_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_5_prs1 <= io_enq_0_prs1;
|
|
slots_5_prs2 <= io_enq_0_prs2;
|
|
slots_5_prd <= io_enq_0_prd;
|
|
slots_5_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_5_src1Ready <=
|
|
_GEN_10
|
|
? io_enq_1_src1Ready
|
|
: _GEN_9
|
|
? io_enq_0_src1Ready
|
|
: valid_5
|
|
& (io_wakeup_1_valid & _src1Wake_T_22 | io_wakeup_0_valid
|
|
& _src1Wake_T_20) | slots_5_src1Ready;
|
|
slots_5_src2Ready <=
|
|
_GEN_10
|
|
? io_enq_1_src2Ready
|
|
: _GEN_9
|
|
? io_enq_0_src2Ready
|
|
: valid_5
|
|
& (io_wakeup_1_valid & _src2Wake_T_22 | io_wakeup_0_valid
|
|
& _src2Wake_T_20) | slots_5_src2Ready;
|
|
if (_GEN_12) begin
|
|
slots_6_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_6_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_6_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_6_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_6_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_6_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_6_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_6_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_6_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_6_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_6_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_6_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_6_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_6_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_6_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_6_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_6_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_6_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_6_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_6_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_6_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_6_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_6_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_6_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_6_prs1 <= io_enq_1_prs1;
|
|
slots_6_prs2 <= io_enq_1_prs2;
|
|
slots_6_prd <= io_enq_1_prd;
|
|
slots_6_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_11) begin
|
|
slots_6_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_6_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_6_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_6_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_6_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_6_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_6_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_6_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_6_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_6_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_6_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_6_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_6_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_6_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_6_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_6_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_6_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_6_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_6_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_6_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_6_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_6_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_6_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_6_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_6_prs1 <= io_enq_0_prs1;
|
|
slots_6_prs2 <= io_enq_0_prs2;
|
|
slots_6_prd <= io_enq_0_prd;
|
|
slots_6_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_6_src1Ready <=
|
|
_GEN_12
|
|
? io_enq_1_src1Ready
|
|
: _GEN_11
|
|
? io_enq_0_src1Ready
|
|
: valid_6
|
|
& (io_wakeup_1_valid & _src1Wake_T_26 | io_wakeup_0_valid
|
|
& _src1Wake_T_24) | slots_6_src1Ready;
|
|
slots_6_src2Ready <=
|
|
_GEN_12
|
|
? io_enq_1_src2Ready
|
|
: _GEN_11
|
|
? io_enq_0_src2Ready
|
|
: valid_6
|
|
& (io_wakeup_1_valid & _src2Wake_T_26 | io_wakeup_0_valid
|
|
& _src2Wake_T_24) | slots_6_src2Ready;
|
|
if (_GEN_14) begin
|
|
slots_7_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_7_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_7_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_7_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_7_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_7_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_7_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_7_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_7_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_7_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_7_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_7_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_7_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_7_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_7_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_7_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_7_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_7_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_7_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_7_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_7_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_7_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_7_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_7_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_7_prs1 <= io_enq_1_prs1;
|
|
slots_7_prs2 <= io_enq_1_prs2;
|
|
slots_7_prd <= io_enq_1_prd;
|
|
slots_7_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_13) begin
|
|
slots_7_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_7_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_7_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_7_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_7_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_7_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_7_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_7_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_7_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_7_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_7_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_7_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_7_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_7_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_7_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_7_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_7_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_7_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_7_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_7_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_7_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_7_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_7_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_7_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_7_prs1 <= io_enq_0_prs1;
|
|
slots_7_prs2 <= io_enq_0_prs2;
|
|
slots_7_prd <= io_enq_0_prd;
|
|
slots_7_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_7_src1Ready <=
|
|
_GEN_14
|
|
? io_enq_1_src1Ready
|
|
: _GEN_13
|
|
? io_enq_0_src1Ready
|
|
: valid_7
|
|
& (io_wakeup_1_valid & _src1Wake_T_30 | io_wakeup_0_valid
|
|
& _src1Wake_T_28) | slots_7_src1Ready;
|
|
slots_7_src2Ready <=
|
|
_GEN_14
|
|
? io_enq_1_src2Ready
|
|
: _GEN_13
|
|
? io_enq_0_src2Ready
|
|
: valid_7
|
|
& (io_wakeup_1_valid & _src2Wake_T_30 | io_wakeup_0_valid
|
|
& _src2Wake_T_28) | slots_7_src2Ready;
|
|
if (_GEN_16) begin
|
|
slots_8_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_8_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_8_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_8_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_8_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_8_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_8_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_8_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_8_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_8_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_8_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_8_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_8_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_8_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_8_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_8_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_8_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_8_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_8_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_8_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_8_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_8_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_8_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_8_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_8_prs1 <= io_enq_1_prs1;
|
|
slots_8_prs2 <= io_enq_1_prs2;
|
|
slots_8_prd <= io_enq_1_prd;
|
|
slots_8_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_15) begin
|
|
slots_8_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_8_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_8_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_8_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_8_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_8_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_8_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_8_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_8_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_8_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_8_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_8_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_8_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_8_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_8_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_8_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_8_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_8_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_8_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_8_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_8_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_8_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_8_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_8_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_8_prs1 <= io_enq_0_prs1;
|
|
slots_8_prs2 <= io_enq_0_prs2;
|
|
slots_8_prd <= io_enq_0_prd;
|
|
slots_8_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_8_src1Ready <=
|
|
_GEN_16
|
|
? io_enq_1_src1Ready
|
|
: _GEN_15
|
|
? io_enq_0_src1Ready
|
|
: valid_8
|
|
& (io_wakeup_1_valid & _src1Wake_T_34 | io_wakeup_0_valid
|
|
& _src1Wake_T_32) | slots_8_src1Ready;
|
|
slots_8_src2Ready <=
|
|
_GEN_16
|
|
? io_enq_1_src2Ready
|
|
: _GEN_15
|
|
? io_enq_0_src2Ready
|
|
: valid_8
|
|
& (io_wakeup_1_valid & _src2Wake_T_34 | io_wakeup_0_valid
|
|
& _src2Wake_T_32) | slots_8_src2Ready;
|
|
if (_GEN_18) begin
|
|
slots_9_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_9_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_9_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_9_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_9_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_9_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_9_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_9_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_9_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_9_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_9_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_9_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_9_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_9_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_9_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_9_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_9_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_9_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_9_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_9_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_9_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_9_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_9_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_9_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_9_prs1 <= io_enq_1_prs1;
|
|
slots_9_prs2 <= io_enq_1_prs2;
|
|
slots_9_prd <= io_enq_1_prd;
|
|
slots_9_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_17) begin
|
|
slots_9_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_9_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_9_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_9_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_9_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_9_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_9_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_9_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_9_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_9_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_9_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_9_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_9_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_9_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_9_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_9_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_9_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_9_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_9_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_9_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_9_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_9_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_9_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_9_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_9_prs1 <= io_enq_0_prs1;
|
|
slots_9_prs2 <= io_enq_0_prs2;
|
|
slots_9_prd <= io_enq_0_prd;
|
|
slots_9_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_9_src1Ready <=
|
|
_GEN_18
|
|
? io_enq_1_src1Ready
|
|
: _GEN_17
|
|
? io_enq_0_src1Ready
|
|
: valid_9
|
|
& (io_wakeup_1_valid & _src1Wake_T_38 | io_wakeup_0_valid
|
|
& _src1Wake_T_36) | slots_9_src1Ready;
|
|
slots_9_src2Ready <=
|
|
_GEN_18
|
|
? io_enq_1_src2Ready
|
|
: _GEN_17
|
|
? io_enq_0_src2Ready
|
|
: valid_9
|
|
& (io_wakeup_1_valid & _src2Wake_T_38 | io_wakeup_0_valid
|
|
& _src2Wake_T_36) | slots_9_src2Ready;
|
|
if (_GEN_20) begin
|
|
slots_10_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_10_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_10_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_10_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_10_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_10_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_10_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_10_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_10_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_10_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_10_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_10_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_10_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_10_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_10_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_10_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_10_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_10_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_10_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_10_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_10_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_10_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_10_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_10_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_10_prs1 <= io_enq_1_prs1;
|
|
slots_10_prs2 <= io_enq_1_prs2;
|
|
slots_10_prd <= io_enq_1_prd;
|
|
slots_10_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_19) begin
|
|
slots_10_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_10_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_10_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_10_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_10_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_10_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_10_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_10_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_10_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_10_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_10_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_10_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_10_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_10_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_10_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_10_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_10_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_10_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_10_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_10_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_10_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_10_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_10_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_10_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_10_prs1 <= io_enq_0_prs1;
|
|
slots_10_prs2 <= io_enq_0_prs2;
|
|
slots_10_prd <= io_enq_0_prd;
|
|
slots_10_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_10_src1Ready <=
|
|
_GEN_20
|
|
? io_enq_1_src1Ready
|
|
: _GEN_19
|
|
? io_enq_0_src1Ready
|
|
: valid_10
|
|
& (io_wakeup_1_valid & _src1Wake_T_42 | io_wakeup_0_valid
|
|
& _src1Wake_T_40) | slots_10_src1Ready;
|
|
slots_10_src2Ready <=
|
|
_GEN_20
|
|
? io_enq_1_src2Ready
|
|
: _GEN_19
|
|
? io_enq_0_src2Ready
|
|
: valid_10
|
|
& (io_wakeup_1_valid & _src2Wake_T_42 | io_wakeup_0_valid
|
|
& _src2Wake_T_40) | slots_10_src2Ready;
|
|
if (_GEN_22) begin
|
|
slots_11_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_11_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_11_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_11_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_11_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_11_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_11_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_11_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_11_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_11_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_11_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_11_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_11_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_11_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_11_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_11_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_11_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_11_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_11_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_11_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_11_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_11_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_11_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_11_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_11_prs1 <= io_enq_1_prs1;
|
|
slots_11_prs2 <= io_enq_1_prs2;
|
|
slots_11_prd <= io_enq_1_prd;
|
|
slots_11_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_21) begin
|
|
slots_11_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_11_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_11_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_11_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_11_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_11_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_11_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_11_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_11_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_11_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_11_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_11_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_11_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_11_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_11_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_11_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_11_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_11_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_11_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_11_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_11_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_11_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_11_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_11_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_11_prs1 <= io_enq_0_prs1;
|
|
slots_11_prs2 <= io_enq_0_prs2;
|
|
slots_11_prd <= io_enq_0_prd;
|
|
slots_11_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_11_src1Ready <=
|
|
_GEN_22
|
|
? io_enq_1_src1Ready
|
|
: _GEN_21
|
|
? io_enq_0_src1Ready
|
|
: valid_11
|
|
& (io_wakeup_1_valid & _src1Wake_T_46 | io_wakeup_0_valid
|
|
& _src1Wake_T_44) | slots_11_src1Ready;
|
|
slots_11_src2Ready <=
|
|
_GEN_22
|
|
? io_enq_1_src2Ready
|
|
: _GEN_21
|
|
? io_enq_0_src2Ready
|
|
: valid_11
|
|
& (io_wakeup_1_valid & _src2Wake_T_46 | io_wakeup_0_valid
|
|
& _src2Wake_T_44) | slots_11_src2Ready;
|
|
if (_GEN_24) begin
|
|
slots_12_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_12_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_12_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_12_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_12_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_12_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_12_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_12_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_12_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_12_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_12_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_12_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_12_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_12_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_12_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_12_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_12_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_12_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_12_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_12_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_12_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_12_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_12_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_12_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_12_prs1 <= io_enq_1_prs1;
|
|
slots_12_prs2 <= io_enq_1_prs2;
|
|
slots_12_prd <= io_enq_1_prd;
|
|
slots_12_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_23) begin
|
|
slots_12_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_12_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_12_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_12_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_12_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_12_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_12_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_12_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_12_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_12_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_12_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_12_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_12_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_12_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_12_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_12_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_12_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_12_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_12_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_12_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_12_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_12_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_12_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_12_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_12_prs1 <= io_enq_0_prs1;
|
|
slots_12_prs2 <= io_enq_0_prs2;
|
|
slots_12_prd <= io_enq_0_prd;
|
|
slots_12_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_12_src1Ready <=
|
|
_GEN_24
|
|
? io_enq_1_src1Ready
|
|
: _GEN_23
|
|
? io_enq_0_src1Ready
|
|
: valid_12
|
|
& (io_wakeup_1_valid & _src1Wake_T_50 | io_wakeup_0_valid
|
|
& _src1Wake_T_48) | slots_12_src1Ready;
|
|
slots_12_src2Ready <=
|
|
_GEN_24
|
|
? io_enq_1_src2Ready
|
|
: _GEN_23
|
|
? io_enq_0_src2Ready
|
|
: valid_12
|
|
& (io_wakeup_1_valid & _src2Wake_T_50 | io_wakeup_0_valid
|
|
& _src2Wake_T_48) | slots_12_src2Ready;
|
|
if (_GEN_26) begin
|
|
slots_13_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_13_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_13_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_13_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_13_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_13_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_13_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_13_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_13_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_13_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_13_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_13_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_13_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_13_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_13_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_13_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_13_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_13_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_13_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_13_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_13_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_13_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_13_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_13_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_13_prs1 <= io_enq_1_prs1;
|
|
slots_13_prs2 <= io_enq_1_prs2;
|
|
slots_13_prd <= io_enq_1_prd;
|
|
slots_13_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_25) begin
|
|
slots_13_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_13_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_13_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_13_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_13_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_13_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_13_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_13_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_13_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_13_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_13_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_13_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_13_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_13_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_13_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_13_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_13_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_13_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_13_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_13_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_13_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_13_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_13_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_13_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_13_prs1 <= io_enq_0_prs1;
|
|
slots_13_prs2 <= io_enq_0_prs2;
|
|
slots_13_prd <= io_enq_0_prd;
|
|
slots_13_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_13_src1Ready <=
|
|
_GEN_26
|
|
? io_enq_1_src1Ready
|
|
: _GEN_25
|
|
? io_enq_0_src1Ready
|
|
: valid_13
|
|
& (io_wakeup_1_valid & _src1Wake_T_54 | io_wakeup_0_valid
|
|
& _src1Wake_T_52) | slots_13_src1Ready;
|
|
slots_13_src2Ready <=
|
|
_GEN_26
|
|
? io_enq_1_src2Ready
|
|
: _GEN_25
|
|
? io_enq_0_src2Ready
|
|
: valid_13
|
|
& (io_wakeup_1_valid & _src2Wake_T_54 | io_wakeup_0_valid
|
|
& _src2Wake_T_52) | slots_13_src2Ready;
|
|
if (_GEN_28) begin
|
|
slots_14_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_14_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_14_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_14_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_14_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_14_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_14_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_14_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_14_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_14_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_14_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_14_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_14_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_14_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_14_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_14_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_14_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_14_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_14_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_14_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_14_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_14_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_14_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_14_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_14_prs1 <= io_enq_1_prs1;
|
|
slots_14_prs2 <= io_enq_1_prs2;
|
|
slots_14_prd <= io_enq_1_prd;
|
|
slots_14_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_27) begin
|
|
slots_14_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_14_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_14_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_14_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_14_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_14_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_14_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_14_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_14_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_14_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_14_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_14_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_14_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_14_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_14_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_14_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_14_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_14_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_14_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_14_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_14_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_14_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_14_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_14_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_14_prs1 <= io_enq_0_prs1;
|
|
slots_14_prs2 <= io_enq_0_prs2;
|
|
slots_14_prd <= io_enq_0_prd;
|
|
slots_14_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_14_src1Ready <=
|
|
_GEN_28
|
|
? io_enq_1_src1Ready
|
|
: _GEN_27
|
|
? io_enq_0_src1Ready
|
|
: valid_14
|
|
& (io_wakeup_1_valid & _src1Wake_T_58 | io_wakeup_0_valid
|
|
& _src1Wake_T_56) | slots_14_src1Ready;
|
|
slots_14_src2Ready <=
|
|
_GEN_28
|
|
? io_enq_1_src2Ready
|
|
: _GEN_27
|
|
? io_enq_0_src2Ready
|
|
: valid_14
|
|
& (io_wakeup_1_valid & _src2Wake_T_58 | io_wakeup_0_valid
|
|
& _src2Wake_T_56) | slots_14_src2Ready;
|
|
if (_GEN_30) begin
|
|
slots_15_decoded_pc <= io_enq_1_decoded_pc;
|
|
slots_15_decoded_inst <= io_enq_1_decoded_inst;
|
|
slots_15_decoded_rs1 <= io_enq_1_decoded_rs1;
|
|
slots_15_decoded_rs2 <= io_enq_1_decoded_rs2;
|
|
slots_15_decoded_funct3 <= io_enq_1_decoded_funct3;
|
|
slots_15_decoded_immI <= io_enq_1_decoded_immI;
|
|
slots_15_decoded_immS <= io_enq_1_decoded_immS;
|
|
slots_15_decoded_immB <= io_enq_1_decoded_immB;
|
|
slots_15_decoded_immU <= io_enq_1_decoded_immU;
|
|
slots_15_decoded_immJ <= io_enq_1_decoded_immJ;
|
|
slots_15_decoded_aluFn <= io_enq_1_decoded_aluFn;
|
|
slots_15_decoded_memWidth <= io_enq_1_decoded_memWidth;
|
|
slots_15_decoded_isLoad <= io_enq_1_decoded_isLoad;
|
|
slots_15_decoded_isStore <= io_enq_1_decoded_isStore;
|
|
slots_15_decoded_isBranch <= io_enq_1_decoded_isBranch;
|
|
slots_15_decoded_isJal <= io_enq_1_decoded_isJal;
|
|
slots_15_decoded_isJalr <= io_enq_1_decoded_isJalr;
|
|
slots_15_decoded_isLui <= io_enq_1_decoded_isLui;
|
|
slots_15_decoded_isAuipc <= io_enq_1_decoded_isAuipc;
|
|
slots_15_decoded_isOpImm <= io_enq_1_decoded_isOpImm;
|
|
slots_15_decoded_isWord <= io_enq_1_decoded_isWord;
|
|
slots_15_decoded_isSystem <= io_enq_1_decoded_isSystem;
|
|
slots_15_decoded_writesRd <= io_enq_1_decoded_writesRd;
|
|
slots_15_decoded_illegal <= io_enq_1_decoded_illegal;
|
|
slots_15_prs1 <= io_enq_1_prs1;
|
|
slots_15_prs2 <= io_enq_1_prs2;
|
|
slots_15_prd <= io_enq_1_prd;
|
|
slots_15_robIdx <= io_enq_1_robIdx;
|
|
end
|
|
else if (_GEN_29) begin
|
|
slots_15_decoded_pc <= io_enq_0_decoded_pc;
|
|
slots_15_decoded_inst <= io_enq_0_decoded_inst;
|
|
slots_15_decoded_rs1 <= io_enq_0_decoded_rs1;
|
|
slots_15_decoded_rs2 <= io_enq_0_decoded_rs2;
|
|
slots_15_decoded_funct3 <= io_enq_0_decoded_funct3;
|
|
slots_15_decoded_immI <= io_enq_0_decoded_immI;
|
|
slots_15_decoded_immS <= io_enq_0_decoded_immS;
|
|
slots_15_decoded_immB <= io_enq_0_decoded_immB;
|
|
slots_15_decoded_immU <= io_enq_0_decoded_immU;
|
|
slots_15_decoded_immJ <= io_enq_0_decoded_immJ;
|
|
slots_15_decoded_aluFn <= io_enq_0_decoded_aluFn;
|
|
slots_15_decoded_memWidth <= io_enq_0_decoded_memWidth;
|
|
slots_15_decoded_isLoad <= io_enq_0_decoded_isLoad;
|
|
slots_15_decoded_isStore <= io_enq_0_decoded_isStore;
|
|
slots_15_decoded_isBranch <= io_enq_0_decoded_isBranch;
|
|
slots_15_decoded_isJal <= io_enq_0_decoded_isJal;
|
|
slots_15_decoded_isJalr <= io_enq_0_decoded_isJalr;
|
|
slots_15_decoded_isLui <= io_enq_0_decoded_isLui;
|
|
slots_15_decoded_isAuipc <= io_enq_0_decoded_isAuipc;
|
|
slots_15_decoded_isOpImm <= io_enq_0_decoded_isOpImm;
|
|
slots_15_decoded_isWord <= io_enq_0_decoded_isWord;
|
|
slots_15_decoded_isSystem <= io_enq_0_decoded_isSystem;
|
|
slots_15_decoded_writesRd <= io_enq_0_decoded_writesRd;
|
|
slots_15_decoded_illegal <= io_enq_0_decoded_illegal;
|
|
slots_15_prs1 <= io_enq_0_prs1;
|
|
slots_15_prs2 <= io_enq_0_prs2;
|
|
slots_15_prd <= io_enq_0_prd;
|
|
slots_15_robIdx <= io_enq_0_robIdx;
|
|
end
|
|
slots_15_src1Ready <=
|
|
_GEN_30
|
|
? io_enq_1_src1Ready
|
|
: _GEN_29
|
|
? io_enq_0_src1Ready
|
|
: valid_15
|
|
& (io_wakeup_1_valid & _src1Wake_T_62 | io_wakeup_0_valid
|
|
& _src1Wake_T_60) | slots_15_src1Ready;
|
|
slots_15_src2Ready <=
|
|
_GEN_30
|
|
? io_enq_1_src2Ready
|
|
: _GEN_29
|
|
? io_enq_0_src2Ready
|
|
: valid_15
|
|
& (io_wakeup_1_valid & _src2Wake_T_62 | io_wakeup_0_valid
|
|
& _src2Wake_T_60) | slots_15_src2Ready;
|
|
end
|
|
end // always @(posedge)
|
|
assign io_enqReady_0 = |freeMask;
|
|
assign io_enqReady_1 = |_io_enqReady_1_T_1;
|
|
assign io_issueValid_0 = |_io_issueValid_1_T;
|
|
assign io_issueValid_1 = |(_io_issueValid_1_T & _io_issueValid_1_T_1);
|
|
assign io_issue_0_decoded_pc =
|
|
(issue0OH[0] ? slots_0_decoded_pc : 64'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_pc : 64'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_pc : 64'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_pc : 64'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_pc : 64'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_pc : 64'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_pc : 64'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_pc : 64'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_pc : 64'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_pc : 64'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_pc : 64'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_pc : 64'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_pc : 64'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_pc : 64'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_pc : 64'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_pc : 64'h0);
|
|
assign io_issue_0_decoded_inst =
|
|
(issue0OH[0] ? slots_0_decoded_inst : 32'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_inst : 32'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_inst : 32'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_inst : 32'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_inst : 32'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_inst : 32'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_inst : 32'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_inst : 32'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_inst : 32'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_inst : 32'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_inst : 32'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_inst : 32'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_inst : 32'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_inst : 32'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_inst : 32'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_inst : 32'h0);
|
|
assign io_issue_0_decoded_rs1 =
|
|
(issue0OH[0] ? slots_0_decoded_rs1 : 5'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_rs1 : 5'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_rs1 : 5'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_rs1 : 5'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_rs1 : 5'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_rs1 : 5'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_rs1 : 5'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_rs1 : 5'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_rs1 : 5'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_rs1 : 5'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_rs1 : 5'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_rs1 : 5'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_rs1 : 5'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_rs1 : 5'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_rs1 : 5'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_rs1 : 5'h0);
|
|
assign io_issue_0_decoded_funct3 =
|
|
(issue0OH[0] ? slots_0_decoded_funct3 : 3'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_funct3 : 3'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_funct3 : 3'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_funct3 : 3'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_funct3 : 3'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_funct3 : 3'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_funct3 : 3'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_funct3 : 3'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_funct3 : 3'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_funct3 : 3'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_funct3 : 3'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_funct3 : 3'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_funct3 : 3'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_funct3 : 3'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_funct3 : 3'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_funct3 : 3'h0);
|
|
assign io_issue_0_decoded_immI =
|
|
(issue0OH[0] ? slots_0_decoded_immI : 64'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_immI : 64'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_immI : 64'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_immI : 64'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_immI : 64'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_immI : 64'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_immI : 64'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_immI : 64'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_immI : 64'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_immI : 64'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_immI : 64'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_immI : 64'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_immI : 64'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_immI : 64'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_immI : 64'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_immI : 64'h0);
|
|
assign io_issue_0_decoded_immS =
|
|
(issue0OH[0] ? slots_0_decoded_immS : 64'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_immS : 64'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_immS : 64'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_immS : 64'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_immS : 64'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_immS : 64'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_immS : 64'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_immS : 64'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_immS : 64'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_immS : 64'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_immS : 64'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_immS : 64'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_immS : 64'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_immS : 64'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_immS : 64'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_immS : 64'h0);
|
|
assign io_issue_0_decoded_immB =
|
|
(issue0OH[0] ? slots_0_decoded_immB : 64'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_immB : 64'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_immB : 64'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_immB : 64'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_immB : 64'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_immB : 64'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_immB : 64'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_immB : 64'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_immB : 64'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_immB : 64'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_immB : 64'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_immB : 64'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_immB : 64'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_immB : 64'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_immB : 64'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_immB : 64'h0);
|
|
assign io_issue_0_decoded_immU =
|
|
(issue0OH[0] ? slots_0_decoded_immU : 64'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_immU : 64'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_immU : 64'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_immU : 64'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_immU : 64'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_immU : 64'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_immU : 64'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_immU : 64'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_immU : 64'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_immU : 64'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_immU : 64'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_immU : 64'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_immU : 64'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_immU : 64'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_immU : 64'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_immU : 64'h0);
|
|
assign io_issue_0_decoded_immJ =
|
|
(issue0OH[0] ? slots_0_decoded_immJ : 64'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_immJ : 64'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_immJ : 64'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_immJ : 64'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_immJ : 64'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_immJ : 64'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_immJ : 64'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_immJ : 64'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_immJ : 64'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_immJ : 64'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_immJ : 64'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_immJ : 64'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_immJ : 64'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_immJ : 64'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_immJ : 64'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_immJ : 64'h0);
|
|
assign io_issue_0_decoded_aluFn =
|
|
(issue0OH[0] ? slots_0_decoded_aluFn : 5'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_aluFn : 5'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_aluFn : 5'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_aluFn : 5'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_aluFn : 5'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_aluFn : 5'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_aluFn : 5'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_aluFn : 5'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_aluFn : 5'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_aluFn : 5'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_aluFn : 5'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_aluFn : 5'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_aluFn : 5'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_aluFn : 5'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_aluFn : 5'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_aluFn : 5'h0);
|
|
assign io_issue_0_decoded_memWidth =
|
|
(issue0OH[0] ? slots_0_decoded_memWidth : 3'h0)
|
|
| (issue0OH[1] ? slots_1_decoded_memWidth : 3'h0)
|
|
| (issue0OH[2] ? slots_2_decoded_memWidth : 3'h0)
|
|
| (issue0OH[3] ? slots_3_decoded_memWidth : 3'h0)
|
|
| (issue0OH[4] ? slots_4_decoded_memWidth : 3'h0)
|
|
| (issue0OH[5] ? slots_5_decoded_memWidth : 3'h0)
|
|
| (issue0OH[6] ? slots_6_decoded_memWidth : 3'h0)
|
|
| (issue0OH[7] ? slots_7_decoded_memWidth : 3'h0)
|
|
| (issue0OH[8] ? slots_8_decoded_memWidth : 3'h0)
|
|
| (issue0OH[9] ? slots_9_decoded_memWidth : 3'h0)
|
|
| (issue0OH[10] ? slots_10_decoded_memWidth : 3'h0)
|
|
| (issue0OH[11] ? slots_11_decoded_memWidth : 3'h0)
|
|
| (issue0OH[12] ? slots_12_decoded_memWidth : 3'h0)
|
|
| (issue0OH[13] ? slots_13_decoded_memWidth : 3'h0)
|
|
| (issue0OH[14] ? slots_14_decoded_memWidth : 3'h0)
|
|
| (issue0OH[15] ? slots_15_decoded_memWidth : 3'h0);
|
|
assign io_issue_0_decoded_isLoad =
|
|
issue0OH[0] & slots_0_decoded_isLoad | issue0OH[1] & slots_1_decoded_isLoad
|
|
| issue0OH[2] & slots_2_decoded_isLoad | issue0OH[3] & slots_3_decoded_isLoad
|
|
| issue0OH[4] & slots_4_decoded_isLoad | issue0OH[5] & slots_5_decoded_isLoad
|
|
| issue0OH[6] & slots_6_decoded_isLoad | issue0OH[7] & slots_7_decoded_isLoad
|
|
| issue0OH[8] & slots_8_decoded_isLoad | issue0OH[9] & slots_9_decoded_isLoad
|
|
| issue0OH[10] & slots_10_decoded_isLoad | issue0OH[11] & slots_11_decoded_isLoad
|
|
| issue0OH[12] & slots_12_decoded_isLoad | issue0OH[13] & slots_13_decoded_isLoad
|
|
| issue0OH[14] & slots_14_decoded_isLoad | issue0OH[15] & slots_15_decoded_isLoad;
|
|
assign io_issue_0_decoded_isStore =
|
|
issue0OH[0] & slots_0_decoded_isStore | issue0OH[1] & slots_1_decoded_isStore
|
|
| issue0OH[2] & slots_2_decoded_isStore | issue0OH[3] & slots_3_decoded_isStore
|
|
| issue0OH[4] & slots_4_decoded_isStore | issue0OH[5] & slots_5_decoded_isStore
|
|
| issue0OH[6] & slots_6_decoded_isStore | issue0OH[7] & slots_7_decoded_isStore
|
|
| issue0OH[8] & slots_8_decoded_isStore | issue0OH[9] & slots_9_decoded_isStore
|
|
| issue0OH[10] & slots_10_decoded_isStore | issue0OH[11] & slots_11_decoded_isStore
|
|
| issue0OH[12] & slots_12_decoded_isStore | issue0OH[13] & slots_13_decoded_isStore
|
|
| issue0OH[14] & slots_14_decoded_isStore | issue0OH[15] & slots_15_decoded_isStore;
|
|
assign io_issue_0_decoded_isBranch =
|
|
issue0OH[0] & slots_0_decoded_isBranch | issue0OH[1] & slots_1_decoded_isBranch
|
|
| issue0OH[2] & slots_2_decoded_isBranch | issue0OH[3] & slots_3_decoded_isBranch
|
|
| issue0OH[4] & slots_4_decoded_isBranch | issue0OH[5] & slots_5_decoded_isBranch
|
|
| issue0OH[6] & slots_6_decoded_isBranch | issue0OH[7] & slots_7_decoded_isBranch
|
|
| issue0OH[8] & slots_8_decoded_isBranch | issue0OH[9] & slots_9_decoded_isBranch
|
|
| issue0OH[10] & slots_10_decoded_isBranch | issue0OH[11] & slots_11_decoded_isBranch
|
|
| issue0OH[12] & slots_12_decoded_isBranch | issue0OH[13] & slots_13_decoded_isBranch
|
|
| issue0OH[14] & slots_14_decoded_isBranch | issue0OH[15] & slots_15_decoded_isBranch;
|
|
assign io_issue_0_decoded_isJal =
|
|
issue0OH[0] & slots_0_decoded_isJal | issue0OH[1] & slots_1_decoded_isJal
|
|
| issue0OH[2] & slots_2_decoded_isJal | issue0OH[3] & slots_3_decoded_isJal
|
|
| issue0OH[4] & slots_4_decoded_isJal | issue0OH[5] & slots_5_decoded_isJal
|
|
| issue0OH[6] & slots_6_decoded_isJal | issue0OH[7] & slots_7_decoded_isJal
|
|
| issue0OH[8] & slots_8_decoded_isJal | issue0OH[9] & slots_9_decoded_isJal
|
|
| issue0OH[10] & slots_10_decoded_isJal | issue0OH[11] & slots_11_decoded_isJal
|
|
| issue0OH[12] & slots_12_decoded_isJal | issue0OH[13] & slots_13_decoded_isJal
|
|
| issue0OH[14] & slots_14_decoded_isJal | issue0OH[15] & slots_15_decoded_isJal;
|
|
assign io_issue_0_decoded_isJalr =
|
|
issue0OH[0] & slots_0_decoded_isJalr | issue0OH[1] & slots_1_decoded_isJalr
|
|
| issue0OH[2] & slots_2_decoded_isJalr | issue0OH[3] & slots_3_decoded_isJalr
|
|
| issue0OH[4] & slots_4_decoded_isJalr | issue0OH[5] & slots_5_decoded_isJalr
|
|
| issue0OH[6] & slots_6_decoded_isJalr | issue0OH[7] & slots_7_decoded_isJalr
|
|
| issue0OH[8] & slots_8_decoded_isJalr | issue0OH[9] & slots_9_decoded_isJalr
|
|
| issue0OH[10] & slots_10_decoded_isJalr | issue0OH[11] & slots_11_decoded_isJalr
|
|
| issue0OH[12] & slots_12_decoded_isJalr | issue0OH[13] & slots_13_decoded_isJalr
|
|
| issue0OH[14] & slots_14_decoded_isJalr | issue0OH[15] & slots_15_decoded_isJalr;
|
|
assign io_issue_0_decoded_isLui =
|
|
issue0OH[0] & slots_0_decoded_isLui | issue0OH[1] & slots_1_decoded_isLui
|
|
| issue0OH[2] & slots_2_decoded_isLui | issue0OH[3] & slots_3_decoded_isLui
|
|
| issue0OH[4] & slots_4_decoded_isLui | issue0OH[5] & slots_5_decoded_isLui
|
|
| issue0OH[6] & slots_6_decoded_isLui | issue0OH[7] & slots_7_decoded_isLui
|
|
| issue0OH[8] & slots_8_decoded_isLui | issue0OH[9] & slots_9_decoded_isLui
|
|
| issue0OH[10] & slots_10_decoded_isLui | issue0OH[11] & slots_11_decoded_isLui
|
|
| issue0OH[12] & slots_12_decoded_isLui | issue0OH[13] & slots_13_decoded_isLui
|
|
| issue0OH[14] & slots_14_decoded_isLui | issue0OH[15] & slots_15_decoded_isLui;
|
|
assign io_issue_0_decoded_isAuipc =
|
|
issue0OH[0] & slots_0_decoded_isAuipc | issue0OH[1] & slots_1_decoded_isAuipc
|
|
| issue0OH[2] & slots_2_decoded_isAuipc | issue0OH[3] & slots_3_decoded_isAuipc
|
|
| issue0OH[4] & slots_4_decoded_isAuipc | issue0OH[5] & slots_5_decoded_isAuipc
|
|
| issue0OH[6] & slots_6_decoded_isAuipc | issue0OH[7] & slots_7_decoded_isAuipc
|
|
| issue0OH[8] & slots_8_decoded_isAuipc | issue0OH[9] & slots_9_decoded_isAuipc
|
|
| issue0OH[10] & slots_10_decoded_isAuipc | issue0OH[11] & slots_11_decoded_isAuipc
|
|
| issue0OH[12] & slots_12_decoded_isAuipc | issue0OH[13] & slots_13_decoded_isAuipc
|
|
| issue0OH[14] & slots_14_decoded_isAuipc | issue0OH[15] & slots_15_decoded_isAuipc;
|
|
assign io_issue_0_decoded_isOpImm =
|
|
issue0OH[0] & slots_0_decoded_isOpImm | issue0OH[1] & slots_1_decoded_isOpImm
|
|
| issue0OH[2] & slots_2_decoded_isOpImm | issue0OH[3] & slots_3_decoded_isOpImm
|
|
| issue0OH[4] & slots_4_decoded_isOpImm | issue0OH[5] & slots_5_decoded_isOpImm
|
|
| issue0OH[6] & slots_6_decoded_isOpImm | issue0OH[7] & slots_7_decoded_isOpImm
|
|
| issue0OH[8] & slots_8_decoded_isOpImm | issue0OH[9] & slots_9_decoded_isOpImm
|
|
| issue0OH[10] & slots_10_decoded_isOpImm | issue0OH[11] & slots_11_decoded_isOpImm
|
|
| issue0OH[12] & slots_12_decoded_isOpImm | issue0OH[13] & slots_13_decoded_isOpImm
|
|
| issue0OH[14] & slots_14_decoded_isOpImm | issue0OH[15] & slots_15_decoded_isOpImm;
|
|
assign io_issue_0_decoded_isWord =
|
|
issue0OH[0] & slots_0_decoded_isWord | issue0OH[1] & slots_1_decoded_isWord
|
|
| issue0OH[2] & slots_2_decoded_isWord | issue0OH[3] & slots_3_decoded_isWord
|
|
| issue0OH[4] & slots_4_decoded_isWord | issue0OH[5] & slots_5_decoded_isWord
|
|
| issue0OH[6] & slots_6_decoded_isWord | issue0OH[7] & slots_7_decoded_isWord
|
|
| issue0OH[8] & slots_8_decoded_isWord | issue0OH[9] & slots_9_decoded_isWord
|
|
| issue0OH[10] & slots_10_decoded_isWord | issue0OH[11] & slots_11_decoded_isWord
|
|
| issue0OH[12] & slots_12_decoded_isWord | issue0OH[13] & slots_13_decoded_isWord
|
|
| issue0OH[14] & slots_14_decoded_isWord | issue0OH[15] & slots_15_decoded_isWord;
|
|
assign io_issue_0_decoded_isSystem =
|
|
issue0OH[0] & slots_0_decoded_isSystem | issue0OH[1] & slots_1_decoded_isSystem
|
|
| issue0OH[2] & slots_2_decoded_isSystem | issue0OH[3] & slots_3_decoded_isSystem
|
|
| issue0OH[4] & slots_4_decoded_isSystem | issue0OH[5] & slots_5_decoded_isSystem
|
|
| issue0OH[6] & slots_6_decoded_isSystem | issue0OH[7] & slots_7_decoded_isSystem
|
|
| issue0OH[8] & slots_8_decoded_isSystem | issue0OH[9] & slots_9_decoded_isSystem
|
|
| issue0OH[10] & slots_10_decoded_isSystem | issue0OH[11] & slots_11_decoded_isSystem
|
|
| issue0OH[12] & slots_12_decoded_isSystem | issue0OH[13] & slots_13_decoded_isSystem
|
|
| issue0OH[14] & slots_14_decoded_isSystem | issue0OH[15] & slots_15_decoded_isSystem;
|
|
assign io_issue_0_decoded_writesRd =
|
|
issue0OH[0] & slots_0_decoded_writesRd | issue0OH[1] & slots_1_decoded_writesRd
|
|
| issue0OH[2] & slots_2_decoded_writesRd | issue0OH[3] & slots_3_decoded_writesRd
|
|
| issue0OH[4] & slots_4_decoded_writesRd | issue0OH[5] & slots_5_decoded_writesRd
|
|
| issue0OH[6] & slots_6_decoded_writesRd | issue0OH[7] & slots_7_decoded_writesRd
|
|
| issue0OH[8] & slots_8_decoded_writesRd | issue0OH[9] & slots_9_decoded_writesRd
|
|
| issue0OH[10] & slots_10_decoded_writesRd | issue0OH[11] & slots_11_decoded_writesRd
|
|
| issue0OH[12] & slots_12_decoded_writesRd | issue0OH[13] & slots_13_decoded_writesRd
|
|
| issue0OH[14] & slots_14_decoded_writesRd | issue0OH[15] & slots_15_decoded_writesRd;
|
|
assign io_issue_0_decoded_illegal =
|
|
issue0OH[0] & slots_0_decoded_illegal | issue0OH[1] & slots_1_decoded_illegal
|
|
| issue0OH[2] & slots_2_decoded_illegal | issue0OH[3] & slots_3_decoded_illegal
|
|
| issue0OH[4] & slots_4_decoded_illegal | issue0OH[5] & slots_5_decoded_illegal
|
|
| issue0OH[6] & slots_6_decoded_illegal | issue0OH[7] & slots_7_decoded_illegal
|
|
| issue0OH[8] & slots_8_decoded_illegal | issue0OH[9] & slots_9_decoded_illegal
|
|
| issue0OH[10] & slots_10_decoded_illegal | issue0OH[11] & slots_11_decoded_illegal
|
|
| issue0OH[12] & slots_12_decoded_illegal | issue0OH[13] & slots_13_decoded_illegal
|
|
| issue0OH[14] & slots_14_decoded_illegal | issue0OH[15] & slots_15_decoded_illegal;
|
|
assign io_issue_0_prs1 =
|
|
(issue0OH[0] ? slots_0_prs1 : 6'h0) | (issue0OH[1] ? slots_1_prs1 : 6'h0)
|
|
| (issue0OH[2] ? slots_2_prs1 : 6'h0) | (issue0OH[3] ? slots_3_prs1 : 6'h0)
|
|
| (issue0OH[4] ? slots_4_prs1 : 6'h0) | (issue0OH[5] ? slots_5_prs1 : 6'h0)
|
|
| (issue0OH[6] ? slots_6_prs1 : 6'h0) | (issue0OH[7] ? slots_7_prs1 : 6'h0)
|
|
| (issue0OH[8] ? slots_8_prs1 : 6'h0) | (issue0OH[9] ? slots_9_prs1 : 6'h0)
|
|
| (issue0OH[10] ? slots_10_prs1 : 6'h0) | (issue0OH[11] ? slots_11_prs1 : 6'h0)
|
|
| (issue0OH[12] ? slots_12_prs1 : 6'h0) | (issue0OH[13] ? slots_13_prs1 : 6'h0)
|
|
| (issue0OH[14] ? slots_14_prs1 : 6'h0) | (issue0OH[15] ? slots_15_prs1 : 6'h0);
|
|
assign io_issue_0_prs2 =
|
|
(issue0OH[0] ? slots_0_prs2 : 6'h0) | (issue0OH[1] ? slots_1_prs2 : 6'h0)
|
|
| (issue0OH[2] ? slots_2_prs2 : 6'h0) | (issue0OH[3] ? slots_3_prs2 : 6'h0)
|
|
| (issue0OH[4] ? slots_4_prs2 : 6'h0) | (issue0OH[5] ? slots_5_prs2 : 6'h0)
|
|
| (issue0OH[6] ? slots_6_prs2 : 6'h0) | (issue0OH[7] ? slots_7_prs2 : 6'h0)
|
|
| (issue0OH[8] ? slots_8_prs2 : 6'h0) | (issue0OH[9] ? slots_9_prs2 : 6'h0)
|
|
| (issue0OH[10] ? slots_10_prs2 : 6'h0) | (issue0OH[11] ? slots_11_prs2 : 6'h0)
|
|
| (issue0OH[12] ? slots_12_prs2 : 6'h0) | (issue0OH[13] ? slots_13_prs2 : 6'h0)
|
|
| (issue0OH[14] ? slots_14_prs2 : 6'h0) | (issue0OH[15] ? slots_15_prs2 : 6'h0);
|
|
assign io_issue_0_prd =
|
|
(issue0OH[0] ? slots_0_prd : 6'h0) | (issue0OH[1] ? slots_1_prd : 6'h0)
|
|
| (issue0OH[2] ? slots_2_prd : 6'h0) | (issue0OH[3] ? slots_3_prd : 6'h0)
|
|
| (issue0OH[4] ? slots_4_prd : 6'h0) | (issue0OH[5] ? slots_5_prd : 6'h0)
|
|
| (issue0OH[6] ? slots_6_prd : 6'h0) | (issue0OH[7] ? slots_7_prd : 6'h0)
|
|
| (issue0OH[8] ? slots_8_prd : 6'h0) | (issue0OH[9] ? slots_9_prd : 6'h0)
|
|
| (issue0OH[10] ? slots_10_prd : 6'h0) | (issue0OH[11] ? slots_11_prd : 6'h0)
|
|
| (issue0OH[12] ? slots_12_prd : 6'h0) | (issue0OH[13] ? slots_13_prd : 6'h0)
|
|
| (issue0OH[14] ? slots_14_prd : 6'h0) | (issue0OH[15] ? slots_15_prd : 6'h0);
|
|
assign io_issue_0_robIdx =
|
|
(issue0OH[0] ? slots_0_robIdx : 6'h0) | (issue0OH[1] ? slots_1_robIdx : 6'h0)
|
|
| (issue0OH[2] ? slots_2_robIdx : 6'h0) | (issue0OH[3] ? slots_3_robIdx : 6'h0)
|
|
| (issue0OH[4] ? slots_4_robIdx : 6'h0) | (issue0OH[5] ? slots_5_robIdx : 6'h0)
|
|
| (issue0OH[6] ? slots_6_robIdx : 6'h0) | (issue0OH[7] ? slots_7_robIdx : 6'h0)
|
|
| (issue0OH[8] ? slots_8_robIdx : 6'h0) | (issue0OH[9] ? slots_9_robIdx : 6'h0)
|
|
| (issue0OH[10] ? slots_10_robIdx : 6'h0) | (issue0OH[11] ? slots_11_robIdx : 6'h0)
|
|
| (issue0OH[12] ? slots_12_robIdx : 6'h0) | (issue0OH[13] ? slots_13_robIdx : 6'h0)
|
|
| (issue0OH[14] ? slots_14_robIdx : 6'h0) | (issue0OH[15] ? slots_15_robIdx : 6'h0);
|
|
assign io_issue_1_decoded_pc =
|
|
(issue1OH[0] ? slots_0_decoded_pc : 64'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_pc : 64'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_pc : 64'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_pc : 64'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_pc : 64'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_pc : 64'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_pc : 64'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_pc : 64'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_pc : 64'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_pc : 64'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_pc : 64'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_pc : 64'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_pc : 64'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_pc : 64'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_pc : 64'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_pc : 64'h0);
|
|
assign io_issue_1_decoded_inst =
|
|
(issue1OH[0] ? slots_0_decoded_inst : 32'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_inst : 32'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_inst : 32'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_inst : 32'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_inst : 32'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_inst : 32'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_inst : 32'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_inst : 32'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_inst : 32'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_inst : 32'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_inst : 32'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_inst : 32'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_inst : 32'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_inst : 32'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_inst : 32'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_inst : 32'h0);
|
|
assign io_issue_1_decoded_rs1 =
|
|
(issue1OH[0] ? slots_0_decoded_rs1 : 5'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_rs1 : 5'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_rs1 : 5'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_rs1 : 5'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_rs1 : 5'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_rs1 : 5'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_rs1 : 5'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_rs1 : 5'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_rs1 : 5'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_rs1 : 5'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_rs1 : 5'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_rs1 : 5'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_rs1 : 5'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_rs1 : 5'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_rs1 : 5'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_rs1 : 5'h0);
|
|
assign io_issue_1_decoded_funct3 =
|
|
(issue1OH[0] ? slots_0_decoded_funct3 : 3'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_funct3 : 3'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_funct3 : 3'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_funct3 : 3'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_funct3 : 3'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_funct3 : 3'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_funct3 : 3'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_funct3 : 3'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_funct3 : 3'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_funct3 : 3'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_funct3 : 3'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_funct3 : 3'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_funct3 : 3'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_funct3 : 3'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_funct3 : 3'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_funct3 : 3'h0);
|
|
assign io_issue_1_decoded_immI =
|
|
(issue1OH[0] ? slots_0_decoded_immI : 64'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_immI : 64'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_immI : 64'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_immI : 64'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_immI : 64'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_immI : 64'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_immI : 64'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_immI : 64'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_immI : 64'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_immI : 64'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_immI : 64'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_immI : 64'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_immI : 64'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_immI : 64'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_immI : 64'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_immI : 64'h0);
|
|
assign io_issue_1_decoded_immS =
|
|
(issue1OH[0] ? slots_0_decoded_immS : 64'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_immS : 64'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_immS : 64'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_immS : 64'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_immS : 64'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_immS : 64'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_immS : 64'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_immS : 64'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_immS : 64'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_immS : 64'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_immS : 64'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_immS : 64'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_immS : 64'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_immS : 64'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_immS : 64'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_immS : 64'h0);
|
|
assign io_issue_1_decoded_immB =
|
|
(issue1OH[0] ? slots_0_decoded_immB : 64'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_immB : 64'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_immB : 64'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_immB : 64'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_immB : 64'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_immB : 64'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_immB : 64'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_immB : 64'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_immB : 64'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_immB : 64'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_immB : 64'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_immB : 64'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_immB : 64'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_immB : 64'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_immB : 64'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_immB : 64'h0);
|
|
assign io_issue_1_decoded_immU =
|
|
(issue1OH[0] ? slots_0_decoded_immU : 64'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_immU : 64'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_immU : 64'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_immU : 64'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_immU : 64'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_immU : 64'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_immU : 64'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_immU : 64'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_immU : 64'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_immU : 64'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_immU : 64'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_immU : 64'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_immU : 64'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_immU : 64'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_immU : 64'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_immU : 64'h0);
|
|
assign io_issue_1_decoded_immJ =
|
|
(issue1OH[0] ? slots_0_decoded_immJ : 64'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_immJ : 64'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_immJ : 64'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_immJ : 64'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_immJ : 64'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_immJ : 64'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_immJ : 64'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_immJ : 64'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_immJ : 64'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_immJ : 64'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_immJ : 64'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_immJ : 64'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_immJ : 64'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_immJ : 64'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_immJ : 64'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_immJ : 64'h0);
|
|
assign io_issue_1_decoded_aluFn =
|
|
(issue1OH[0] ? slots_0_decoded_aluFn : 5'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_aluFn : 5'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_aluFn : 5'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_aluFn : 5'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_aluFn : 5'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_aluFn : 5'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_aluFn : 5'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_aluFn : 5'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_aluFn : 5'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_aluFn : 5'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_aluFn : 5'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_aluFn : 5'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_aluFn : 5'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_aluFn : 5'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_aluFn : 5'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_aluFn : 5'h0);
|
|
assign io_issue_1_decoded_memWidth =
|
|
(issue1OH[0] ? slots_0_decoded_memWidth : 3'h0)
|
|
| (issue1OH[1] ? slots_1_decoded_memWidth : 3'h0)
|
|
| (issue1OH[2] ? slots_2_decoded_memWidth : 3'h0)
|
|
| (issue1OH[3] ? slots_3_decoded_memWidth : 3'h0)
|
|
| (issue1OH[4] ? slots_4_decoded_memWidth : 3'h0)
|
|
| (issue1OH[5] ? slots_5_decoded_memWidth : 3'h0)
|
|
| (issue1OH[6] ? slots_6_decoded_memWidth : 3'h0)
|
|
| (issue1OH[7] ? slots_7_decoded_memWidth : 3'h0)
|
|
| (issue1OH[8] ? slots_8_decoded_memWidth : 3'h0)
|
|
| (issue1OH[9] ? slots_9_decoded_memWidth : 3'h0)
|
|
| (issue1OH[10] ? slots_10_decoded_memWidth : 3'h0)
|
|
| (issue1OH[11] ? slots_11_decoded_memWidth : 3'h0)
|
|
| (issue1OH[12] ? slots_12_decoded_memWidth : 3'h0)
|
|
| (issue1OH[13] ? slots_13_decoded_memWidth : 3'h0)
|
|
| (issue1OH[14] ? slots_14_decoded_memWidth : 3'h0)
|
|
| (issue1OH[15] ? slots_15_decoded_memWidth : 3'h0);
|
|
assign io_issue_1_decoded_isLoad =
|
|
issue1OH[0] & slots_0_decoded_isLoad | issue1OH[1] & slots_1_decoded_isLoad
|
|
| issue1OH[2] & slots_2_decoded_isLoad | issue1OH[3] & slots_3_decoded_isLoad
|
|
| issue1OH[4] & slots_4_decoded_isLoad | issue1OH[5] & slots_5_decoded_isLoad
|
|
| issue1OH[6] & slots_6_decoded_isLoad | issue1OH[7] & slots_7_decoded_isLoad
|
|
| issue1OH[8] & slots_8_decoded_isLoad | issue1OH[9] & slots_9_decoded_isLoad
|
|
| issue1OH[10] & slots_10_decoded_isLoad | issue1OH[11] & slots_11_decoded_isLoad
|
|
| issue1OH[12] & slots_12_decoded_isLoad | issue1OH[13] & slots_13_decoded_isLoad
|
|
| issue1OH[14] & slots_14_decoded_isLoad | issue1OH[15] & slots_15_decoded_isLoad;
|
|
assign io_issue_1_decoded_isStore =
|
|
issue1OH[0] & slots_0_decoded_isStore | issue1OH[1] & slots_1_decoded_isStore
|
|
| issue1OH[2] & slots_2_decoded_isStore | issue1OH[3] & slots_3_decoded_isStore
|
|
| issue1OH[4] & slots_4_decoded_isStore | issue1OH[5] & slots_5_decoded_isStore
|
|
| issue1OH[6] & slots_6_decoded_isStore | issue1OH[7] & slots_7_decoded_isStore
|
|
| issue1OH[8] & slots_8_decoded_isStore | issue1OH[9] & slots_9_decoded_isStore
|
|
| issue1OH[10] & slots_10_decoded_isStore | issue1OH[11] & slots_11_decoded_isStore
|
|
| issue1OH[12] & slots_12_decoded_isStore | issue1OH[13] & slots_13_decoded_isStore
|
|
| issue1OH[14] & slots_14_decoded_isStore | issue1OH[15] & slots_15_decoded_isStore;
|
|
assign io_issue_1_decoded_isBranch =
|
|
issue1OH[0] & slots_0_decoded_isBranch | issue1OH[1] & slots_1_decoded_isBranch
|
|
| issue1OH[2] & slots_2_decoded_isBranch | issue1OH[3] & slots_3_decoded_isBranch
|
|
| issue1OH[4] & slots_4_decoded_isBranch | issue1OH[5] & slots_5_decoded_isBranch
|
|
| issue1OH[6] & slots_6_decoded_isBranch | issue1OH[7] & slots_7_decoded_isBranch
|
|
| issue1OH[8] & slots_8_decoded_isBranch | issue1OH[9] & slots_9_decoded_isBranch
|
|
| issue1OH[10] & slots_10_decoded_isBranch | issue1OH[11] & slots_11_decoded_isBranch
|
|
| issue1OH[12] & slots_12_decoded_isBranch | issue1OH[13] & slots_13_decoded_isBranch
|
|
| issue1OH[14] & slots_14_decoded_isBranch | issue1OH[15] & slots_15_decoded_isBranch;
|
|
assign io_issue_1_decoded_isJal =
|
|
issue1OH[0] & slots_0_decoded_isJal | issue1OH[1] & slots_1_decoded_isJal
|
|
| issue1OH[2] & slots_2_decoded_isJal | issue1OH[3] & slots_3_decoded_isJal
|
|
| issue1OH[4] & slots_4_decoded_isJal | issue1OH[5] & slots_5_decoded_isJal
|
|
| issue1OH[6] & slots_6_decoded_isJal | issue1OH[7] & slots_7_decoded_isJal
|
|
| issue1OH[8] & slots_8_decoded_isJal | issue1OH[9] & slots_9_decoded_isJal
|
|
| issue1OH[10] & slots_10_decoded_isJal | issue1OH[11] & slots_11_decoded_isJal
|
|
| issue1OH[12] & slots_12_decoded_isJal | issue1OH[13] & slots_13_decoded_isJal
|
|
| issue1OH[14] & slots_14_decoded_isJal | issue1OH[15] & slots_15_decoded_isJal;
|
|
assign io_issue_1_decoded_isJalr =
|
|
issue1OH[0] & slots_0_decoded_isJalr | issue1OH[1] & slots_1_decoded_isJalr
|
|
| issue1OH[2] & slots_2_decoded_isJalr | issue1OH[3] & slots_3_decoded_isJalr
|
|
| issue1OH[4] & slots_4_decoded_isJalr | issue1OH[5] & slots_5_decoded_isJalr
|
|
| issue1OH[6] & slots_6_decoded_isJalr | issue1OH[7] & slots_7_decoded_isJalr
|
|
| issue1OH[8] & slots_8_decoded_isJalr | issue1OH[9] & slots_9_decoded_isJalr
|
|
| issue1OH[10] & slots_10_decoded_isJalr | issue1OH[11] & slots_11_decoded_isJalr
|
|
| issue1OH[12] & slots_12_decoded_isJalr | issue1OH[13] & slots_13_decoded_isJalr
|
|
| issue1OH[14] & slots_14_decoded_isJalr | issue1OH[15] & slots_15_decoded_isJalr;
|
|
assign io_issue_1_decoded_isLui =
|
|
issue1OH[0] & slots_0_decoded_isLui | issue1OH[1] & slots_1_decoded_isLui
|
|
| issue1OH[2] & slots_2_decoded_isLui | issue1OH[3] & slots_3_decoded_isLui
|
|
| issue1OH[4] & slots_4_decoded_isLui | issue1OH[5] & slots_5_decoded_isLui
|
|
| issue1OH[6] & slots_6_decoded_isLui | issue1OH[7] & slots_7_decoded_isLui
|
|
| issue1OH[8] & slots_8_decoded_isLui | issue1OH[9] & slots_9_decoded_isLui
|
|
| issue1OH[10] & slots_10_decoded_isLui | issue1OH[11] & slots_11_decoded_isLui
|
|
| issue1OH[12] & slots_12_decoded_isLui | issue1OH[13] & slots_13_decoded_isLui
|
|
| issue1OH[14] & slots_14_decoded_isLui | issue1OH[15] & slots_15_decoded_isLui;
|
|
assign io_issue_1_decoded_isAuipc =
|
|
issue1OH[0] & slots_0_decoded_isAuipc | issue1OH[1] & slots_1_decoded_isAuipc
|
|
| issue1OH[2] & slots_2_decoded_isAuipc | issue1OH[3] & slots_3_decoded_isAuipc
|
|
| issue1OH[4] & slots_4_decoded_isAuipc | issue1OH[5] & slots_5_decoded_isAuipc
|
|
| issue1OH[6] & slots_6_decoded_isAuipc | issue1OH[7] & slots_7_decoded_isAuipc
|
|
| issue1OH[8] & slots_8_decoded_isAuipc | issue1OH[9] & slots_9_decoded_isAuipc
|
|
| issue1OH[10] & slots_10_decoded_isAuipc | issue1OH[11] & slots_11_decoded_isAuipc
|
|
| issue1OH[12] & slots_12_decoded_isAuipc | issue1OH[13] & slots_13_decoded_isAuipc
|
|
| issue1OH[14] & slots_14_decoded_isAuipc | issue1OH[15] & slots_15_decoded_isAuipc;
|
|
assign io_issue_1_decoded_isOpImm =
|
|
issue1OH[0] & slots_0_decoded_isOpImm | issue1OH[1] & slots_1_decoded_isOpImm
|
|
| issue1OH[2] & slots_2_decoded_isOpImm | issue1OH[3] & slots_3_decoded_isOpImm
|
|
| issue1OH[4] & slots_4_decoded_isOpImm | issue1OH[5] & slots_5_decoded_isOpImm
|
|
| issue1OH[6] & slots_6_decoded_isOpImm | issue1OH[7] & slots_7_decoded_isOpImm
|
|
| issue1OH[8] & slots_8_decoded_isOpImm | issue1OH[9] & slots_9_decoded_isOpImm
|
|
| issue1OH[10] & slots_10_decoded_isOpImm | issue1OH[11] & slots_11_decoded_isOpImm
|
|
| issue1OH[12] & slots_12_decoded_isOpImm | issue1OH[13] & slots_13_decoded_isOpImm
|
|
| issue1OH[14] & slots_14_decoded_isOpImm | issue1OH[15] & slots_15_decoded_isOpImm;
|
|
assign io_issue_1_decoded_isWord =
|
|
issue1OH[0] & slots_0_decoded_isWord | issue1OH[1] & slots_1_decoded_isWord
|
|
| issue1OH[2] & slots_2_decoded_isWord | issue1OH[3] & slots_3_decoded_isWord
|
|
| issue1OH[4] & slots_4_decoded_isWord | issue1OH[5] & slots_5_decoded_isWord
|
|
| issue1OH[6] & slots_6_decoded_isWord | issue1OH[7] & slots_7_decoded_isWord
|
|
| issue1OH[8] & slots_8_decoded_isWord | issue1OH[9] & slots_9_decoded_isWord
|
|
| issue1OH[10] & slots_10_decoded_isWord | issue1OH[11] & slots_11_decoded_isWord
|
|
| issue1OH[12] & slots_12_decoded_isWord | issue1OH[13] & slots_13_decoded_isWord
|
|
| issue1OH[14] & slots_14_decoded_isWord | issue1OH[15] & slots_15_decoded_isWord;
|
|
assign io_issue_1_decoded_isSystem =
|
|
issue1OH[0] & slots_0_decoded_isSystem | issue1OH[1] & slots_1_decoded_isSystem
|
|
| issue1OH[2] & slots_2_decoded_isSystem | issue1OH[3] & slots_3_decoded_isSystem
|
|
| issue1OH[4] & slots_4_decoded_isSystem | issue1OH[5] & slots_5_decoded_isSystem
|
|
| issue1OH[6] & slots_6_decoded_isSystem | issue1OH[7] & slots_7_decoded_isSystem
|
|
| issue1OH[8] & slots_8_decoded_isSystem | issue1OH[9] & slots_9_decoded_isSystem
|
|
| issue1OH[10] & slots_10_decoded_isSystem | issue1OH[11] & slots_11_decoded_isSystem
|
|
| issue1OH[12] & slots_12_decoded_isSystem | issue1OH[13] & slots_13_decoded_isSystem
|
|
| issue1OH[14] & slots_14_decoded_isSystem | issue1OH[15] & slots_15_decoded_isSystem;
|
|
assign io_issue_1_decoded_writesRd =
|
|
issue1OH[0] & slots_0_decoded_writesRd | issue1OH[1] & slots_1_decoded_writesRd
|
|
| issue1OH[2] & slots_2_decoded_writesRd | issue1OH[3] & slots_3_decoded_writesRd
|
|
| issue1OH[4] & slots_4_decoded_writesRd | issue1OH[5] & slots_5_decoded_writesRd
|
|
| issue1OH[6] & slots_6_decoded_writesRd | issue1OH[7] & slots_7_decoded_writesRd
|
|
| issue1OH[8] & slots_8_decoded_writesRd | issue1OH[9] & slots_9_decoded_writesRd
|
|
| issue1OH[10] & slots_10_decoded_writesRd | issue1OH[11] & slots_11_decoded_writesRd
|
|
| issue1OH[12] & slots_12_decoded_writesRd | issue1OH[13] & slots_13_decoded_writesRd
|
|
| issue1OH[14] & slots_14_decoded_writesRd | issue1OH[15] & slots_15_decoded_writesRd;
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assign io_issue_1_decoded_illegal =
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issue1OH[0] & slots_0_decoded_illegal | issue1OH[1] & slots_1_decoded_illegal
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| issue1OH[2] & slots_2_decoded_illegal | issue1OH[3] & slots_3_decoded_illegal
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| issue1OH[4] & slots_4_decoded_illegal | issue1OH[5] & slots_5_decoded_illegal
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| issue1OH[6] & slots_6_decoded_illegal | issue1OH[7] & slots_7_decoded_illegal
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| issue1OH[8] & slots_8_decoded_illegal | issue1OH[9] & slots_9_decoded_illegal
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| issue1OH[10] & slots_10_decoded_illegal | issue1OH[11] & slots_11_decoded_illegal
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| issue1OH[12] & slots_12_decoded_illegal | issue1OH[13] & slots_13_decoded_illegal
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| issue1OH[14] & slots_14_decoded_illegal | issue1OH[15] & slots_15_decoded_illegal;
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assign io_issue_1_prs1 =
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(issue1OH[0] ? slots_0_prs1 : 6'h0) | (issue1OH[1] ? slots_1_prs1 : 6'h0)
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| (issue1OH[2] ? slots_2_prs1 : 6'h0) | (issue1OH[3] ? slots_3_prs1 : 6'h0)
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| (issue1OH[4] ? slots_4_prs1 : 6'h0) | (issue1OH[5] ? slots_5_prs1 : 6'h0)
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| (issue1OH[6] ? slots_6_prs1 : 6'h0) | (issue1OH[7] ? slots_7_prs1 : 6'h0)
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| (issue1OH[8] ? slots_8_prs1 : 6'h0) | (issue1OH[9] ? slots_9_prs1 : 6'h0)
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| (issue1OH[10] ? slots_10_prs1 : 6'h0) | (issue1OH[11] ? slots_11_prs1 : 6'h0)
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| (issue1OH[12] ? slots_12_prs1 : 6'h0) | (issue1OH[13] ? slots_13_prs1 : 6'h0)
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| (issue1OH[14] ? slots_14_prs1 : 6'h0) | (issue1OH[15] ? slots_15_prs1 : 6'h0);
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assign io_issue_1_prs2 =
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(issue1OH[0] ? slots_0_prs2 : 6'h0) | (issue1OH[1] ? slots_1_prs2 : 6'h0)
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| (issue1OH[2] ? slots_2_prs2 : 6'h0) | (issue1OH[3] ? slots_3_prs2 : 6'h0)
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| (issue1OH[4] ? slots_4_prs2 : 6'h0) | (issue1OH[5] ? slots_5_prs2 : 6'h0)
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| (issue1OH[6] ? slots_6_prs2 : 6'h0) | (issue1OH[7] ? slots_7_prs2 : 6'h0)
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| (issue1OH[8] ? slots_8_prs2 : 6'h0) | (issue1OH[9] ? slots_9_prs2 : 6'h0)
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| (issue1OH[10] ? slots_10_prs2 : 6'h0) | (issue1OH[11] ? slots_11_prs2 : 6'h0)
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| (issue1OH[12] ? slots_12_prs2 : 6'h0) | (issue1OH[13] ? slots_13_prs2 : 6'h0)
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| (issue1OH[14] ? slots_14_prs2 : 6'h0) | (issue1OH[15] ? slots_15_prs2 : 6'h0);
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assign io_issue_1_prd =
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(issue1OH[0] ? slots_0_prd : 6'h0) | (issue1OH[1] ? slots_1_prd : 6'h0)
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| (issue1OH[2] ? slots_2_prd : 6'h0) | (issue1OH[3] ? slots_3_prd : 6'h0)
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| (issue1OH[4] ? slots_4_prd : 6'h0) | (issue1OH[5] ? slots_5_prd : 6'h0)
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| (issue1OH[6] ? slots_6_prd : 6'h0) | (issue1OH[7] ? slots_7_prd : 6'h0)
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| (issue1OH[8] ? slots_8_prd : 6'h0) | (issue1OH[9] ? slots_9_prd : 6'h0)
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| (issue1OH[10] ? slots_10_prd : 6'h0) | (issue1OH[11] ? slots_11_prd : 6'h0)
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| (issue1OH[12] ? slots_12_prd : 6'h0) | (issue1OH[13] ? slots_13_prd : 6'h0)
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| (issue1OH[14] ? slots_14_prd : 6'h0) | (issue1OH[15] ? slots_15_prd : 6'h0);
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assign io_issue_1_robIdx =
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(issue1OH[0] ? slots_0_robIdx : 6'h0) | (issue1OH[1] ? slots_1_robIdx : 6'h0)
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| (issue1OH[2] ? slots_2_robIdx : 6'h0) | (issue1OH[3] ? slots_3_robIdx : 6'h0)
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| (issue1OH[4] ? slots_4_robIdx : 6'h0) | (issue1OH[5] ? slots_5_robIdx : 6'h0)
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| (issue1OH[6] ? slots_6_robIdx : 6'h0) | (issue1OH[7] ? slots_7_robIdx : 6'h0)
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| (issue1OH[8] ? slots_8_robIdx : 6'h0) | (issue1OH[9] ? slots_9_robIdx : 6'h0)
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| (issue1OH[10] ? slots_10_robIdx : 6'h0) | (issue1OH[11] ? slots_11_robIdx : 6'h0)
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| (issue1OH[12] ? slots_12_robIdx : 6'h0) | (issue1OH[13] ? slots_13_robIdx : 6'h0)
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| (issue1OH[14] ? slots_14_robIdx : 6'h0) | (issue1OH[15] ? slots_15_robIdx : 6'h0);
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endmodule
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