// Generated by CIRCT firtool-1.139.0 module CSRFile( input clock, reset, io_cmd_valid, input [11:0] io_cmd_addr, input [2:0] io_cmd_cmd, input [63:0] io_cmd_rs1, input [4:0] io_cmd_zimm, input [11:0] io_readAddr, output [63:0] io_rdata, input io_trap, input [63:0] io_trapPc, io_trapCause, output [63:0] io_satp, io_mtvec, io_mepc ); reg [63:0] cycle; reg [63:0] mstatus; reg [63:0] mtvecReg; reg [63:0] mepcReg; reg [63:0] mcause; reg [63:0] mtval; reg [63:0] medeleg; reg [63:0] mideleg; reg [63:0] mie; reg [63:0] mip; reg [63:0] sstatus; reg [63:0] stvec; reg [63:0] sepc; reg [63:0] scause; reg [63:0] stval; reg [63:0] sscratch; reg [63:0] satpReg; always @(posedge clock) begin if (reset) begin cycle <= 64'h0; mstatus <= 64'h0; mtvecReg <= 64'h0; mepcReg <= 64'h0; mcause <= 64'h0; mtval <= 64'h0; medeleg <= 64'h0; mideleg <= 64'h0; mie <= 64'h0; mip <= 64'h0; sstatus <= 64'h0; stvec <= 64'h0; sepc <= 64'h0; scause <= 64'h0; stval <= 64'h0; sscratch <= 64'h0; satpReg <= 64'h0; end else begin automatic logic _GEN; automatic logic _GEN_0; automatic logic _GEN_1; automatic logic _GEN_2; automatic logic _GEN_3; automatic logic _GEN_4; automatic logic _GEN_5; automatic logic _GEN_6 = io_cmd_addr == 12'h343; automatic logic _GEN_7 = io_cmd_addr == 12'h344; automatic logic _GEN_8 = io_cmd_addr == 12'h100; automatic logic _GEN_9 = io_cmd_addr == 12'h105; automatic logic _GEN_10 = io_cmd_addr == 12'h140; automatic logic _GEN_11 = io_cmd_addr == 12'h141; automatic logic _GEN_12 = io_cmd_addr == 12'h142; automatic logic _GEN_13 = io_cmd_addr == 12'h143; automatic logic _GEN_14 = io_cmd_addr == 12'h180; automatic logic [63:0] _GEN_15; automatic logic [63:0] writeOld; automatic logic [63:0] operand; automatic logic [63:0] _next_T_1; automatic logic [63:0] _next_T_3; automatic logic [3:0][63:0] _GEN_16; automatic logic [63:0] next; automatic logic _GEN_17; _GEN = io_cmd_addr == 12'h300; _GEN_0 = io_cmd_addr == 12'h302; _GEN_1 = io_cmd_addr == 12'h303; _GEN_2 = io_cmd_addr == 12'h304; _GEN_3 = io_cmd_addr == 12'h305; _GEN_4 = io_cmd_addr == 12'h341; _GEN_5 = io_cmd_addr == 12'h342; _GEN_15 = io_cmd_addr == 12'h301 ? 64'h800000000014112D : _GEN_0 ? medeleg : _GEN_1 ? mideleg : _GEN_2 ? mie : _GEN_3 ? mtvecReg : _GEN_4 ? mepcReg : _GEN_5 ? mcause : _GEN_6 ? mtval : _GEN_7 ? mip : _GEN_8 ? sstatus : _GEN_9 ? stvec : _GEN_10 ? sscratch : _GEN_11 ? sepc : _GEN_12 ? scause : _GEN_13 ? stval : _GEN_14 ? satpReg : io_cmd_addr == 12'hF14 | io_cmd_addr != 12'hC00 ? 64'h0 : cycle; writeOld = _GEN ? mstatus : _GEN_15; operand = io_cmd_cmd[2] ? {59'h0, io_cmd_zimm} : io_cmd_rs1; _next_T_1 = writeOld | operand; _next_T_3 = writeOld & ~operand; _GEN_16 = {{_next_T_3}, {_next_T_1}, {operand}, {writeOld}}; next = _GEN_16[io_cmd_cmd[1:0]]; _GEN_17 = io_cmd_valid & (|io_cmd_cmd); cycle <= cycle + 64'h1; if (_GEN_17 & _GEN) mstatus <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | ~_GEN_3) begin end else mtvecReg <= next; if (io_trap) begin mepcReg <= io_trapPc; mcause <= io_trapCause; end else begin if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | ~_GEN_4) begin end else mepcReg <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | ~_GEN_5) begin end else mcause <= next; end if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | ~_GEN_6) begin end else mtval <= next; if (~_GEN_17 | _GEN | ~_GEN_0) begin end else begin automatic logic [3:0][63:0] _GEN_18; _GEN_18 = {{_next_T_3}, {_next_T_1}, {operand}, {_GEN_15}}; medeleg <= _GEN_18[io_cmd_cmd[1:0]]; end if (~_GEN_17 | _GEN | _GEN_0 | ~_GEN_1) begin end else mideleg <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | ~_GEN_2) begin end else mie <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | ~_GEN_7) begin end else mip <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | ~_GEN_8) begin end else sstatus <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_8 | ~_GEN_9) begin end else stvec <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | ~_GEN_11) begin end else sepc <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | ~_GEN_12) begin end else scause <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | ~_GEN_13) begin end else stval <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_8 | _GEN_9 | ~_GEN_10) begin end else sscratch <= next; if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | _GEN_13 | ~_GEN_14) begin end else satpReg <= next; end end // always @(posedge) assign io_rdata = io_readAddr == 12'h300 ? mstatus : io_readAddr == 12'h301 ? 64'h800000000014112D : io_readAddr == 12'h302 ? medeleg : io_readAddr == 12'h303 ? mideleg : io_readAddr == 12'h304 ? mie : io_readAddr == 12'h305 ? mtvecReg : io_readAddr == 12'h341 ? mepcReg : io_readAddr == 12'h342 ? mcause : io_readAddr == 12'h343 ? mtval : io_readAddr == 12'h344 ? mip : io_readAddr == 12'h100 ? sstatus : io_readAddr == 12'h105 ? stvec : io_readAddr == 12'h140 ? sscratch : io_readAddr == 12'h141 ? sepc : io_readAddr == 12'h142 ? scause : io_readAddr == 12'h143 ? stval : io_readAddr == 12'h180 ? satpReg : io_readAddr == 12'hF14 | io_readAddr != 12'hC00 ? 64'h0 : cycle; assign io_satp = satpReg; assign io_mtvec = mtvecReg; assign io_mepc = mepcReg; endmodule