467 lines
12 KiB
Markdown
467 lines
12 KiB
Markdown
# RISC-V RV64G 双发射乱序处理器架构设计
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## 目标规格
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- **ISA**: RV64IMAFD (RV64G without C extension)
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- **Issue Width**: 双发射（每周期2条指令）
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- **Physical Registers**: 64个物理寄存器
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- **Branch Predictor**: Gshare
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- **Memory**: Sv39分页，分离的L1 ICache/DCache
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- **Pipeline**: 11级流水线，乱序执行
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---
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## 1. 流水线架构
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### 流水线阶段
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```
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┌─────┐ ┌─────┐ ┌────┐ ┌────┐ ┌────┐ ┌────┐ ┌─────┐ ┌─────┐ ┌─────┐ ┌────┐
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│ IF1 │ → │ IF2 │ → │ ID │ → │ RN │ → │ DP │ → │ IS │ → │ EX1 │ → │ EX2 │ → │ MEM │ → │ WB │ → │ CM │
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└─────┘ └─────┘ └────┘ └────┘ └────┘ └────┘ └─────┘ └─────┘ └─────┘ └────┘
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TLB ICache Decode Rename Dispatch Issue Execute Execute DCache Write Commit
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BPU 2-way Access Back ROB
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```
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### 各阶段功能
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1. **IF1 (Instruction Fetch 1)**
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- PC生成与选择
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- ITLB查询（虚拟地址 → 物理地址）
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- Gshare分支预测
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- 取两条指令（双发射）
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2. **IF2 (Instruction Fetch 2)**
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- ICache访问（64B缓存行）
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- 指令对齐与缓冲
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3. **ID (Instruction Decode)**
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- 双路译码器（每周期译码2条指令）
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- 指令类型识别
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- 立即数生成
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- 依赖分析（RAW检测）
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4. **RN (Rename)**
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- 寄存器重命名（32逻辑寄存器 → 64物理寄存器）
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- 空闲列表(Free List)管理
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- 重命名表(Rename Map Table)更新
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- ROB分配
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5. **DP (Dispatch)**
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- 分发到保留站(Reservation Station)
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- 根据指令类型选择功能单元队列
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6. **IS (Issue)**
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- 从保留站唤醒就绪指令
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- 乱序发射到执行单元
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- 读取物理寄存器文件
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7. **EX1 (Execute 1)**
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- ALU运算
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- 分支计算
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- 地址生成（load/store）
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- 浮点运算第一阶段
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8. **EX2 (Execute 2)**
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- 多周期运算完成
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- 浮点运算完成
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- 分支结果检查
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9. **MEM (Memory)**
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- DTLB查询
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- DCache访问
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- Load/Store执行
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- Store Buffer管理
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10. **WB (Write Back)**
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- 写回物理寄存器
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- 唤醒依赖指令
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- 更新ROB状态
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11. **CM (Commit)**
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- ROB按序提交
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- 架构状态更新
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- 异常/中断处理
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- 物理寄存器释放
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---
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## 2. 核心部件设计
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### 2.1 前端 (Front-End)
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#### Gshare 分支预测器
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```
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├── Global History Register (GHR): 12-bit
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├── Pattern History Table (PHT): 4096 entries × 2-bit saturating counter
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├── Branch Target Buffer (BTB): 512 entries
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│ ├── Tag: 20-bit
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│ ├── Target Address: 64-bit
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│ └── Valid bit
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└── Return Address Stack (RAS): 16 entries
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```
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**Gshare索引计算**: `index = (PC[13:2] XOR GHR[11:0])`
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要求：Branch Target Buffer大小可配置；Return Address Stack大小可配置
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#### ICache
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```
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├── Capacity: 32 KB
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├── Associativity: 4-way set-associative
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├── Line Size: 64 bytes
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├── Sets: 128
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└── Replacement: Pseudo-LRU
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```
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要求：Capacity大小可配置；Associativity大小可配置
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#### ITLB
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```
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├── Entries: 32 (Fully associative)
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├── Page Size: 4KB (Sv39)
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├── Replacement: LRU
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└── Support: Mega pages (2MB), Giga pages (1GB)
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```
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要求：Entries大小可配置
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### 2.2 乱序执行核心
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#### 重命名逻辑
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```
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Rename Map Table (RMT)
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├── Arch Regs: 32 (x0-x31)
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├── Phys Regs: 64 (p0-p63)
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└── Mapping: arch_reg → phys_reg
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Free List
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├── Available physical registers
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└── FIFO allocation
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Committed Map Table (CMT)
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└── For precise exception recovery
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```
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#### Reorder Buffer (ROB)
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```
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├── Entries: 64
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├── Fields per entry:
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│ ├── Valid
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│ ├── PC
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│ ├── Instruction Type
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│ ├── Destination Physical Register
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│ ├── Old Physical Register (for freeing)
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│ ├── Exception Info
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│ ├── Completed
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│ └── Branch Mispredict
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├── Head Pointer (commit)
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└── Tail Pointer (allocate)
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```
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要求：Entries可配置
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#### Reservation Stations
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```
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Integer RS
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├── Entries: 16
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└── ALU, Branch, Integer Multiply/Divide
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Load/Store RS
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├── Entries: 12
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└── Address generation, Memory ops
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FP RS
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├── Entries: 16
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└── FP Add, FP Multiply, FP Divide
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```
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#### Physical Register File
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```
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Integer PRF
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├── Registers: 64 × 64-bit
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└── Read Ports: 4 (dual-issue × 2 operands)
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└── Write Ports: 2 (dual-issue)
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FP PRF
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├── Registers: 64 × 64-bit
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└── Read Ports: 4
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└── Write Ports: 2
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```
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### 2.3 执行单元
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```
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├── ALU0: Integer ALU (ADD, SUB, AND, OR, XOR, SLT, etc.)
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├── ALU1: Integer ALU
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├── Branch Unit: Branch comparison
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├── AGU: Address Generation Unit (Load/Store)
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├── MDU: Multiply/Divide Unit (3-cycle latency for MUL, iterative for DIV)
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├── FPU0: FP Add/Sub (4-cycle latency)
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├── FPU1: FP Multiply (5-cycle latency)
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└── FPU2: FP Divide/Sqrt (iterative, variable latency)
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```
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### 2.4 后端 (Memory Subsystem)
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#### DCache
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```
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├── Capacity: 32 KB
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├── Associativity: 8-way set-associative
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├── Line Size: 64 bytes
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├── Sets: 64
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├── Replacement: Pseudo-LRU
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├── Write Policy: Write-back
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└── MSHR: 4 entries (Miss Status Holding Registers)
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```
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要求：Capacity大小可配置；Associativity大小可配置
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#### DTLB
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```
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├── Entries: 32 (Fully associative)
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├── Page Size: 4KB (Sv39)
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├── Replacement: LRU
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└── Support: Mega pages (2MB), Giga pages (1GB)
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```
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要求：Entries大小可配置
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#### MMU (Sv39)
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```
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├── Virtual Address: 39-bit
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├── Physical Address: 56-bit (RISC-V spec allows up to 56)
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├── Page Table Walker:
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│ ├── 3-level page table
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│ ├── Hardware page table walk
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│ └── PTE cache (8 entries per level)
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└── CSR Support:
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├── satp (Supervisor Address Translation and Protection)
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├── sstatus, sie, sip, stvec
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└── sepc, scause, stval, sscratch
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```
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#### Load/Store Queue
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```
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Load Queue (LQ)
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├── Entries: 16
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└── Track in-flight loads
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Store Queue (SQ)
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├── Entries: 16
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├── Store-to-Load forwarding
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└── Drain on fence/commit
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```
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要求：Entries大小可配置
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### 2.5 提交阶段
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```
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Commit Logic
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├── Commit Width: 2 instructions per cycle
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├── In-order commit from ROB head
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├── Exception handling:
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│ ├── Flush pipeline
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│ ├── Restore architectural state from CMT
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│ └── Free speculative physical registers
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└── Branch mispredict recovery:
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├── Flush younger instructions
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├── Restore RMT from ROB checkpoint
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└── Redirect fetch
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```
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---
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## 3. 数据通路
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### 3.1 指令流
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```
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PC → ITLB → ICache → Instruction Buffer → Decoder (×2) → Rename →
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Dispatch → Reservation Stations → Issue → Execute → Write Back → ROB → Commit
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```
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### 3.2 数据流
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```
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Read PRF → Execute → Write Result → Broadcast (Bypass) → Write PRF → Update ROB
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└→ Wakeup dependent instructions
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```
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### 3.3 控制流
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```
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Branch Predictor → Speculative Fetch → Execute Branch → Compare →
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[Match: Continue] / [Mispredict: Flush + Redirect]
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```
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---
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## 4. 关键设计决策
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### 4.1 双发射策略
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- **静态配对**: 在ID阶段检查指令间依赖
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- **限制**: 不允许同时发射两条分支指令、两条访存指令
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- **对齐**: 指令对必须来自连续的PC
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### 4.2 物理寄存器分配
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- **64个物理寄存器**: 32个用于映射当前架构状态，32个用于投机执行
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- **回收时机**: 指令提交时，释放旧的物理寄存器
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### 4.3 分支预测恢复
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- **检查点机制**: 每条分支在RN阶段创建RMT快照
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- **恢复**: 分支错误预测时，恢复到该分支的RMT快照
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### 4.4 内存一致性
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- **顺序模型**: RISC-V Weak Memory Order (RVWMO)
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- **Load乱序**: 可以越过Store执行（需要地址消歧）
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- **Store Buffer**: Store指令提交后写入，按序释放到Cache
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### 4.5 异常处理
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- **精确异常**: 通过ROB实现
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- **异常类型**:
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- Page Fault (ITLB/DTLB miss)
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- Illegal Instruction
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- Misaligned Access
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- Breakpoint
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- System Call
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---
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## 5. 性能参数估算
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| 指标 | 目标值 |
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|------|--------|
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| IPC (理想) | 1.8-2.0 |
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| IPC (实际) | 1.2-1.5 (考虑分支错误、Cache miss) |
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| 分支预测准确率 | >90% (Gshare) |
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| ICache命中率 | >95% |
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| DCache命中率 | >90% |
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| TLB命中率 | >98% |
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| 频率目标 | 100-200 MHz (FPGA) |
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---
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## 6. Linux启动需求
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要成功启动Linux，CPU必须支持：
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### 6.1 特权级
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- **M-mode** (Machine): 最高特权级，处理异常/中断
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- **S-mode** (Supervisor): Linux内核运行在此
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- **U-mode** (User): 用户程序
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### 6.2 必需的CSR
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```
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Machine Mode:
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- mstatus, misa, medeleg, mideleg
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- mtvec, mepc, mcause, mtval
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- mip, mie, mtime, mtimecmp
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Supervisor Mode:
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- sstatus, stvec, sepc, scause, stval
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- satp (MMU配置)
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- sip, sie
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Counters:
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- cycle, time, instret
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```
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### 6.3 中断/异常
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- Timer interrupt (CLINT)
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- External interrupt (PLIC)
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- Software interrupt
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- 所有RISC-V异常类型
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### 6.4 原子指令 (A扩展)
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- LR/SC (Load-Reserved/Store-Conditional)
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- AMO (Atomic Memory Operations): AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR, AMOMIN, AMOMAX
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### 6.5 外设接口
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- UART (串口输出)
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- CLINT (核心本地中断器)
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- PLIC (平台级中断控制器)
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---
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## 7. 验证策略
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### 7.1 单元测试
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- 每个模块的功能验证
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- Chisel Unit Tests
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### 7.2 ISA测试
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- riscv-tests (官方ISA测试套件)
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- rv64ui, rv64um, rv64ua, rv64uf, rv64ud
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### 7.3 随机测试
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- riscv-torture (随机指令生成)
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### 7.4 系统测试
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- CoreMark, Dhrystone (性能基准测试)
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- Linux boot (最终目标)
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---
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## 8. Chisel实现模块划分
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```
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src/main/scala/
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├── common/
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│ ├── Consts.scala // 常量定义
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│ ├── Parameters.scala // 参数配置
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│ └── Bundles.scala // 数据结构定义
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├── frontend/
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│ ├── ICache.scala
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│ ├── ITLB.scala
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│ ├── BranchPredictor.scala // Gshare
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│ ├── BTB.scala
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│ ├── RAS.scala
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│ └── Frontend.scala // 前端顶层
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├── decode/
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│ ├── Decoder.scala
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│ └── IDStage.scala
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├── rename/
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│ ├── RenameTable.scala
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│ ├── FreeList.scala
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│ ├── ROB.scala
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│ └── RenameStage.scala
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├── issue/
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│ ├── ReservationStation.scala
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│ ├── IssueQueue.scala
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│ └── IssueStage.scala
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├── execute/
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│ ├── ALU.scala
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│ ├── BranchUnit.scala
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│ ├── Multiplier.scala
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│ ├── Divider.scala
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│ ├── FPU.scala
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│ └── ExecStage.scala
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├── memory/
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│ ├── DCache.scala
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│ ├── DTLB.scala
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│ ├── MMU.scala
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│ ├── LSU.scala // Load/Store Unit
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│ ├── LoadQueue.scala
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│ ├── StoreQueue.scala
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│ └── MemStage.scala
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├── writeback/
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│ └── WriteBackStage.scala
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├── commit/
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│ └── CommitStage.scala
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├── regfile/
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│ └── PhysicalRegFile.scala
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├── csr/
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│ ├── CSRFile.scala
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│ └── PrivilegeControl.scala
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└── Core.scala // 处理器顶层
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```
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---
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## 9. 参考资料
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- **RISC-V Spec**: https://riscv.org/technical/specifications/
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- **Sv39 Paging**: RISC-V Privileged Spec Chapter 4
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- **Gshare Predictor**: "Two-Level Adaptive Training Branch Prediction" (Yeh & Patt, 1991)
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- **BOOM Processor**: Berkeley Out-of-Order Machine (参考设计)
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- **Rocket Chip**: 顺序发射RISC-V处理器（前端参考）
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