39 lines
1.3 KiB
Systemverilog
39 lines
1.3 KiB
Systemverilog
// Generated by CIRCT firtool-1.139.0
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// Users can define 'STOP_COND' to add an extra gate to stop conditions.
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`ifndef STOP_COND_
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`ifdef STOP_COND
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`define STOP_COND_ (`STOP_COND)
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`else // STOP_COND
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`define STOP_COND_ 1
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`endif // STOP_COND
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`endif // not def STOP_COND_
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// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing.
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`ifndef ASSERT_VERBOSE_COND_
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`ifdef ASSERT_VERBOSE_COND
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`define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND)
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`else // ASSERT_VERBOSE_COND
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`define ASSERT_VERBOSE_COND_ 1
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`endif // ASSERT_VERBOSE_COND
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`endif // not def ASSERT_VERBOSE_COND_
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module DCache_Verification_Assert();
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`ifndef SYNTHESIS
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always @(posedge DCache.clock) begin
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if (~DCache.reset & DCache.io_reqValid
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& (|((DCache._storeEndSet_T_6
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? 3'h0
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: DCache._storeEndSet_T_4
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? 3'h4
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: DCache._storeEndSet_T_2 ? 3'h2 : {2'h0, DCache._storeEndSet_T})
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- 3'h1 & DCache.io_req_addr[2:0]))) begin
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if (`ASSERT_VERBOSE_COND_)
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$error("Assertion failed: DCache received misaligned request; LSU must trap before DCache\n");
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if (`STOP_COND_)
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$fatal;
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end
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end // always @(posedge)
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`endif // not def SYNTHESIS
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endmodule
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