39 lines
1.5 KiB
Systemverilog
39 lines
1.5 KiB
Systemverilog
// Generated by CIRCT firtool-1.139.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module OoOBackend_Verification();
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`ifndef SYNTHESIS
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always @(posedge OoOBackend.clock) begin
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automatic logic [63:0] _GEN;
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_GEN =
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OoOBackend.memSlot
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? OoOBackend.issue_io_out_1_decoded_pc
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: OoOBackend.issue_io_out_0_decoded_pc;
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if ((`PRINTF_COND_) & OoOBackend._storeEnq_T & _GEN < 64'h80000050
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& ~OoOBackend.reset)
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$fwrite(32'h80000002,
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"[mem-issue] pc=0x%x inst=0x%x isLoad=%d isStore=%d prs1=%d src1=0x%x immS=0x%x addr=0x%x ready=%d\n",
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_GEN,
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OoOBackend.memSlot
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? OoOBackend.issue_io_out_1_decoded_inst
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: OoOBackend.issue_io_out_0_decoded_inst, OoOBackend._layer_probe_0,
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OoOBackend._layer_probe_1,
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OoOBackend.memSlot
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? OoOBackend.issue_io_out_1_prs1
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: OoOBackend.issue_io_out_0_prs1, OoOBackend.memSrc1,
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OoOBackend._layer_probe, OoOBackend.memAddr,
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OoOBackend.memSlot
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? OoOBackend.issue_io_outReady_1
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: OoOBackend.issue_io_outReady_0);
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end // always @(posedge)
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`endif // not def SYNTHESIS
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endmodule
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