20 lines
401 B
Systemverilog
20 lines
401 B
Systemverilog
// Generated by CIRCT firtool-1.139.0
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module PrivilegeControl(
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input clock,
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reset,
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input [1:0] io_nextPriv,
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input io_setPriv,
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output [1:0] io_priv
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);
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reg [1:0] privReg;
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always @(posedge clock) begin
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if (reset)
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privReg <= 2'h3;
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else if (io_setPriv)
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privReg <= io_nextPriv;
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end // always @(posedge)
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assign io_priv = privReg;
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endmodule
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