feat: implement privileged mode support
This commit is contained in:
abnerhexu
93
sim/results/privileged_test_results.txt
Normal file
93
sim/results/privileged_test_results.txt
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@@ -0,0 +1,93 @@
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Running privileged RISC-V tests...
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=================================
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rv64mi-p-breakpoint: exit=0 PASS
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rv64mi-p-csr: exit=0 PASS
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rv64mi-p-illegal: exit=0 PASS
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rv64mi-p-instret_overflow: exit=1 FAIL
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[5] FLUSH exception=0 mtvec=0x0 mepc=0x0 mcause=0x0 frontend_pc=0x80000008
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[65] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x0
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[66] CSR commit slot0=1 slot1=0 addr=0x744 cmd=5 next=0x800000e8 mtvec=0x800000e8
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[71] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800000e8
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[72] CSR commit slot0=1 slot1=0 addr=0x180 cmd=5 next=0x800000f8 mtvec=0x800000f8
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[77] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800000f8
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[83] CSR commit slot0=1 slot1=0 addr=0x3b0 cmd=1 next=0x0 mtvec=0x8000011c
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[86] CSR commit slot0=1 slot1=0 addr=0x3a0 cmd=1 next=0x0 mtvec=0x8000011c
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[87] CSR commit slot0=1 slot1=0 addr=0x304 cmd=5 next=0x1f mtvec=0x8000011c
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[92] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x8000011c
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[93] CSR commit slot0=1 slot1=0 addr=0x302 cmd=5 next=0x80000134 mtvec=0x80000134
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[95] CSR commit slot0=1 slot1=0 addr=0x303 cmd=5 next=0x0 mtvec=0x80000134
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[101] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x80000134
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[105] FLUSH exception=0 mtvec=0x80000004 mepc=0x0 mcause=0x0 frontend_pc=0x80000158
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[114] FLUSH exception=0 mtvec=0x80000004 mepc=0x0 mcause=0x0 frontend_pc=0x80000170
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[120] CSR commit slot0=1 slot1=0 addr=0x300 cmd=5 next=0x0 mtvec=0x80000004
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[126] CSR commit slot0=1 slot1=0 addr=0x300 cmd=2 next=0x0 mtvec=0x80000004
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[130] CSR commit slot0=1 slot1=0 addr=0x341 cmd=1 next=0x0 mtvec=0x80000004
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[133] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001a0 mcause=0x0 frontend_pc=0x800001a8
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[141] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x80000004
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[142] FLUSH exception=1 mtvec=0x800001b0 mepc=0x800001a0 mcause=0x0 frontend_pc=0x800001b8
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[147] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800001b0
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[150] FLUSH exception=1 mtvec=0x80000004 mepc=0x800001ac mcause=0x2 frontend_pc=0x800001c0
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[171] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001b8 mcause=0x2 frontend_pc=0x80000038
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[177] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001b8 mcause=0x2 frontend_pc=0x80000200
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[193] FLUSH exception=1 mtvec=0x80000004 mepc=0x800001b8 mcause=0x2 frontend_pc=0x800001f0
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[205] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001e4 mcause=0xb frontend_pc=0x80000028
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[213] STORE addr=0x80001000 data=0x5 size=2
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Loaded segment: paddr=0x80000000 size=576
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Loaded segment: paddr=0x80001000 size=72
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ELF loaded: entry=0x80000000
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[213] TEST FAILED: error code 2
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rv64mi-p-ld-misaligned: exit=0 PASS
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rv64mi-p-lh-misaligned: exit=0 PASS
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rv64mi-p-lw-misaligned: exit=0 PASS
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rv64mi-p-ma_addr: exit=0 PASS
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rv64mi-p-ma_fetch: exit=0 PASS
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rv64mi-p-mcsr: exit=1 FAIL
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[5] FLUSH exception=0 mtvec=0x0 mepc=0x0 mcause=0x0 frontend_pc=0x80000008
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[63] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x0
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[65] CSR commit slot0=1 slot1=0 addr=0x744 cmd=5 next=0x0 mtvec=0x800000e4
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[69] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800000e4
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[71] CSR commit slot0=1 slot1=0 addr=0x180 cmd=5 next=0x0 mtvec=0x800000f4
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[75] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x800000f4
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[81] CSR commit slot0=1 slot1=0 addr=0x3b0 cmd=1 next=0x0 mtvec=0x80000118
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[84] CSR commit slot0=1 slot1=0 addr=0x3a0 cmd=1 next=0x0 mtvec=0x80000118
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[86] CSR commit slot0=1 slot1=0 addr=0x304 cmd=5 next=0x0 mtvec=0x80000118
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[90] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x80000118
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[92] CSR commit slot0=1 slot1=0 addr=0x302 cmd=5 next=0x0 mtvec=0x80000130
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[93] CSR commit slot0=1 slot1=0 addr=0x303 cmd=5 next=0x0 mtvec=0x80000130
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[99] CSR commit slot0=1 slot1=0 addr=0x305 cmd=1 next=0x0 mtvec=0x80000130
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[104] FLUSH exception=0 mtvec=0x80000004 mepc=0x0 mcause=0x0 frontend_pc=0x80000150
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[111] FLUSH exception=0 mtvec=0x80000004 mepc=0x0 mcause=0x0 frontend_pc=0x80000170
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[117] CSR commit slot0=1 slot1=0 addr=0x300 cmd=5 next=0x0 mtvec=0x80000004
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[121] CSR commit slot0=1 slot1=0 addr=0x300 cmd=2 next=0x0 mtvec=0x80000004
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[126] CSR commit slot0=1 slot1=0 addr=0x341 cmd=1 next=0x0 mtvec=0x80000004
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[129] FLUSH exception=0 mtvec=0x80000004 mepc=0x8000019c mcause=0x0 frontend_pc=0x800001a0
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[149] FLUSH exception=1 mtvec=0x80000004 mepc=0x8000019c mcause=0x0 frontend_pc=0x800001c8
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[167] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001c0 mcause=0x2 frontend_pc=0x80000030
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[175] FLUSH exception=0 mtvec=0x80000004 mepc=0x800001c0 mcause=0x2 frontend_pc=0x80000038
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[185] STORE addr=0x80001000 data=0x53b size=2
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Loaded segment: paddr=0x80000000 size=572
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Loaded segment: paddr=0x80001000 size=72
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ELF loaded: entry=0x80000000
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[185] TEST FAILED: error code 669
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rv64mi-p-pmpaddr: exit=0 PASS
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rv64mi-p-sbreak: exit=0 PASS
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rv64mi-p-scall: exit=0 PASS
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rv64mi-p-sd-misaligned: exit=0 PASS
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rv64mi-p-sh-misaligned: exit=0 PASS
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rv64mi-p-sw-misaligned: exit=0 PASS
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rv64mi-p-zicntr: exit=0 PASS
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rv64si-p-csr: exit=0 PASS
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rv64si-p-dirty: exit=124 TIMEOUT
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rv64si-p-icache-alias: exit=124 TIMEOUT
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rv64si-p-ma_fetch: exit=0 PASS
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rv64si-p-sbreak: exit=0 PASS
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rv64si-p-scall: exit=0 PASS
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rv64si-p-wfi: exit=0 PASS
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rv64ui-p-fence_i: exit=0 PASS
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=================================
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Summary:
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PASS: 21
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FAIL: 2
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TIMEOUT: 2
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TOTAL: 25
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95
sim/results/test_results.txt
Normal file
95
sim/results/test_results.txt
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@@ -0,0 +1,95 @@
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Running RISC-V tests...
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====================
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rv64ui-p-add: PASS
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rv64ui-p-addi: PASS
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rv64ui-p-addiw: PASS
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rv64ui-p-addw: PASS
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rv64ui-p-and: PASS
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rv64ui-p-andi: PASS
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rv64ui-p-auipc: PASS
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rv64ui-p-beq: PASS
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rv64ui-p-bge: PASS
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rv64ui-p-bgeu: PASS
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rv64ui-p-blt: PASS
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rv64ui-p-bltu: PASS
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rv64ui-p-bne: PASS
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rv64ui-p-fence_i: PASS
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rv64ui-p-jal: PASS
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rv64ui-p-jalr: PASS
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rv64ui-p-lb: PASS
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rv64ui-p-lbu: PASS
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rv64ui-p-ld: PASS
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rv64ui-p-ld_st: PASS
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rv64ui-p-lh: PASS
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rv64ui-p-lhu: PASS
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rv64ui-p-lui: PASS
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rv64ui-p-lw: PASS
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rv64ui-p-lwu: PASS
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rv64ui-p-ma_data: FAIL
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rv64ui-p-or: PASS
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rv64ui-p-ori: PASS
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rv64ui-p-sb: PASS
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rv64ui-p-sd: PASS
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rv64ui-p-sh: PASS
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rv64ui-p-simple: PASS
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rv64ui-p-sll: PASS
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rv64ui-p-slli: PASS
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rv64ui-p-slliw: PASS
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rv64ui-p-sllw: PASS
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rv64ui-p-slt: PASS
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rv64ui-p-slti: PASS
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rv64ui-p-sltiu: PASS
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rv64ui-p-sltu: PASS
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rv64ui-p-sra: PASS
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rv64ui-p-srai: PASS
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rv64ui-p-sraiw: PASS
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rv64ui-p-sraw: PASS
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rv64ui-p-srl: PASS
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rv64ui-p-srli: PASS
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rv64ui-p-srliw: PASS
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rv64ui-p-srlw: PASS
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rv64ui-p-st_ld: PASS
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rv64ui-p-sub: PASS
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rv64ui-p-subw: PASS
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rv64ui-p-sw: PASS
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rv64ui-p-xor: PASS
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rv64ui-p-xori: PASS
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rv64um-p-div: PASS
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rv64um-p-divu: PASS
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rv64um-p-divuw: PASS
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rv64um-p-divw: PASS
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rv64um-p-mul: PASS
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rv64um-p-mulh: PASS
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rv64um-p-mulhsu: PASS
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rv64um-p-mulhu: PASS
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rv64um-p-mulw: PASS
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rv64um-p-rem: PASS
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rv64um-p-remu: PASS
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rv64um-p-remuw: PASS
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rv64um-p-remw: PASS
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rv64ua-p-amoadd_d: PASS
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rv64ua-p-amoadd_w: PASS
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rv64ua-p-amoand_d: PASS
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rv64ua-p-amoand_w: PASS
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rv64ua-p-amomax_d: PASS
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rv64ua-p-amomaxu_d: PASS
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rv64ua-p-amomaxu_w: PASS
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rv64ua-p-amomax_w: PASS
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rv64ua-p-amomin_d: PASS
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rv64ua-p-amominu_d: PASS
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rv64ua-p-amominu_w: PASS
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rv64ua-p-amomin_w: PASS
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rv64ua-p-amoor_d: PASS
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rv64ua-p-amoor_w: PASS
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rv64ua-p-amoswap_d: PASS
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rv64ua-p-amoswap_w: PASS
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rv64ua-p-amoxor_d: PASS
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rv64ua-p-amoxor_w: PASS
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rv64ua-p-lrsc: PASS
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====================
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Summary:
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PASS: 85
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FAIL: 1
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TIMEOUT: 0
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TOTAL: 86
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28
sim/scripts/run_opensbi.sh
Executable file
28
sim/scripts/run_opensbi.sh
Executable file
@@ -0,0 +1,28 @@
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#!/bin/bash
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set -u
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TESTBENCH="../verilator/obj_dir/VCore"
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OPENSBI_BIN="${OPENSBI_BIN:-../../opensbi/build/platform/generic/firmware/fw_payload.elf}"
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TIMEOUT_SECONDS="${TIMEOUT_SECONDS:-10}"
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if [ ! -x "$TESTBENCH" ]; then
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echo "Error: Testbench not found. Run 'make -C sim/verilator compile' first."
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exit 1
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fi
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if [ ! -f "$OPENSBI_BIN" ]; then
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echo "Error: OpenSBI payload not found: $OPENSBI_BIN"
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echo "Set OPENSBI_BIN to a firmware ELF path."
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exit 2
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fi
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echo "Running OpenSBI payload: $OPENSBI_BIN"
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timeout "${TIMEOUT_SECONDS}s" "$TESTBENCH" "$OPENSBI_BIN"
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exitcode=$?
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if [ "$exitcode" -eq 124 ]; then
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echo "OpenSBI run timed out"
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exit 124
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fi
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exit "$exitcode"
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75
sim/scripts/run_privileged_tests.sh
Executable file
75
sim/scripts/run_privileged_tests.sh
Executable file
@@ -0,0 +1,75 @@
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#!/bin/bash
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set -u
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TESTBENCH="../verilator/obj_dir/VCore"
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TESTS_DIR="../../riscv-tests/isa"
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RESULTS_DIR="../results"
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RESULTS_FILE="$RESULTS_DIR/privileged_test_results.txt"
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TIMEOUT_SECONDS="${TIMEOUT_SECONDS:-5}"
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mkdir -p "$RESULTS_DIR"
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if [ ! -x "$TESTBENCH" ]; then
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echo "Error: Testbench not found. Run 'make -C sim/verilator compile' first."
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exit 1
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fi
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echo "Running privileged RISC-V tests..." > "$RESULTS_FILE"
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echo "=================================" >> "$RESULTS_FILE"
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PASS=0
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FAIL=0
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TIMEOUT=0
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shopt -s nullglob
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tests=(
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"$TESTS_DIR"/rv64mi-p-*
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"$TESTS_DIR"/rv64si-p-*
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"$TESTS_DIR"/rv64ui-p-fence_i
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)
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for test in "${tests[@]}"; do
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[[ "$test" == *.dump ]] && continue
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[ ! -f "$test" ] && continue
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testname=$(basename "$test")
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printf "Running %s... " "$testname"
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output=$(timeout "${TIMEOUT_SECONDS}s" "$TESTBENCH" "$test" 2>&1)
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exitcode=$?
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if [ "$exitcode" -eq 0 ]; then
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echo "PASS"
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echo "$testname: exit=0 PASS" >> "$RESULTS_FILE"
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PASS=$((PASS + 1))
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elif [ "$exitcode" -eq 124 ]; then
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echo "TIMEOUT"
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echo "$testname: exit=124 TIMEOUT" >> "$RESULTS_FILE"
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TIMEOUT=$((TIMEOUT + 1))
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else
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echo "FAIL (exit code $exitcode)"
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echo "$testname: exit=$exitcode FAIL" >> "$RESULTS_FILE"
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printf '%s\n' "$output" >> "$RESULTS_FILE"
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FAIL=$((FAIL + 1))
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fi
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done
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TOTAL=$((PASS + FAIL + TIMEOUT))
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{
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echo ""
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echo "================================="
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echo "Summary:"
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echo " PASS: $PASS"
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echo " FAIL: $FAIL"
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echo " TIMEOUT: $TIMEOUT"
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echo " TOTAL: $TOTAL"
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} >> "$RESULTS_FILE"
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echo ""
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echo "Summary:"
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echo " PASS: $PASS"
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echo " FAIL: $FAIL"
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echo " TIMEOUT: $TIMEOUT"
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echo " TOTAL: $TOTAL"
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echo ""
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echo "Results saved to $RESULTS_FILE"
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@@ -2,7 +2,7 @@
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TESTBENCH="../verilator/obj_dir/VCore"
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TESTS_DIR="../../riscv-tests/isa"
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RESULTS_FILE="test_results.txt"
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RESULTS_FILE="../results/test_results.txt"
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if [ ! -x "$TESTBENCH" ]; then
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echo "Error: Testbench not found. Run 'make compile' first."
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4
sim/tests/EcallDelegationTest.scala
Normal file
4
sim/tests/EcallDelegationTest.scala
Normal file
@@ -0,0 +1,4 @@
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// Verilator scenario checklist:
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// 1. Set medeleg bit 8 and execute ecall from U-mode.
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// 2. Expect delegation to S-mode handler when S support is enabled.
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// 3. Clear delegation and verify ecall from U-mode traps to M-mode.
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4
sim/tests/InterruptEnableTest.scala
Normal file
4
sim/tests/InterruptEnableTest.scala
Normal file
@@ -0,0 +1,4 @@
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// Verilator scenario checklist:
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// 1. Toggle MSI, MTI, and MEI pending sources.
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// 2. Verify enable bits gate interrupt injection.
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// 3. Verify MEI > MTI > MSI priority and S-mode delegation bits.
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5
sim/tests/PrivilegeTransitionTest.scala
Normal file
5
sim/tests/PrivilegeTransitionTest.scala
Normal file
@@ -0,0 +1,5 @@
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// Verilator scenario checklist:
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// 1. Start in M-mode after reset.
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// 2. Configure mstatus.MPP=S and mepc to an S-mode entry point.
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// 3. Execute mret and verify the redirected PC equals mepc.
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// 4. Execute an S-mode ecall path and verify trap state is recoverable.
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4
sim/tests/SfenceTest.scala
Normal file
4
sim/tests/SfenceTest.scala
Normal file
@@ -0,0 +1,4 @@
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// Verilator scenario checklist:
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// 1. sfence.vma in U-mode raises illegal instruction.
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// 2. sfence.vma in S/M-mode flushes DTLB state.
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// 3. fence.i invalidates ICache and flushes younger instructions.
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4
sim/tests/XretFlushTest.scala
Normal file
4
sim/tests/XretFlushTest.scala
Normal file
@@ -0,0 +1,4 @@
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// Verilator scenario checklist:
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// 1. Execute mret and sret with younger instructions in flight.
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// 2. Verify commit emits flush and redirect.
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// 3. Verify younger side effects are squashed.
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3
sim/tests/exception/MisalignedTest.scala
Normal file
3
sim/tests/exception/MisalignedTest.scala
Normal file
@@ -0,0 +1,3 @@
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// Verilator scenario checklist:
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// 1. Instruction fetch with pc[1:0] != 0 raises instruction address misaligned.
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// 2. Load/store addresses not aligned to access size raise load/store address misaligned.
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4
sim/tests/exception/PageFaultTest.scala
Normal file
4
sim/tests/exception/PageFaultTest.scala
Normal file
@@ -0,0 +1,4 @@
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// Verilator scenario checklist:
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// 1. Unmapped instruction fetch raises instruction page fault.
|
||||
// 2. Unmapped load/store raises load/store page fault.
|
||||
// 3. U/S permission violations raise page fault instead of access fault.
|
||||
@@ -20,7 +20,7 @@ endif
|
||||
SBT = env SBT_OPTS="-Dsbt.boot.directory=/tmp/sbt-boot -Dsbt.ivy.home=/tmp/sbt-ivy" COURSIER_CACHE=/tmp/coursier-cache sbt
|
||||
|
||||
CHISEL_DIR = ../..
|
||||
OOO ?= 0
|
||||
OOO ?= 1
|
||||
ifeq ($(OOO),1)
|
||||
RUN_MAIN = CoreOoO
|
||||
GENERATED_DIR = $(CHISEL_DIR)/generated-ooo
|
||||
|
||||
@@ -206,7 +206,8 @@ int main(int argc, char** argv) {
|
||||
core->rootp->Core__DOT__frontend__DOT__icache__DOT__missAddr,
|
||||
(unsigned)core->rootp->Core__DOT__fetchValid,
|
||||
(unsigned)core->rootp->Core__DOT__fetchReady,
|
||||
(unsigned)core->rootp->Core__DOT___frontend_io_outValid,
|
||||
(unsigned)(core->rootp->Core__DOT__frontend__DOT__faultPending |
|
||||
core->rootp->Core__DOT__frontend__DOT___icache_io_respValid),
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT___issue_io_inReady_0,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__count,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__freeMask,
|
||||
@@ -255,18 +256,16 @@ int main(int argc, char** argv) {
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__issue0OH,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__issue1OH);
|
||||
fprintf(stderr,
|
||||
"complete: valid=%u/%u idx0=%u exc=%u/%u mis=%u/%u cause=0x%lx/0x%lx redirect=0x%lx/0x%lx\n",
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeValid_0,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeValid_1,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeIdx_0,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeException_0,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeException_1,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeMispredict_0,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeMispredict_1,
|
||||
(uint64_t)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeCause_0,
|
||||
(uint64_t)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeCause_1,
|
||||
(uint64_t)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeRedirectPc_0,
|
||||
(uint64_t)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeRedirectPc_1);
|
||||
"complete: valid=%u/%u idx0=%u exc=%u/%u cause=0x%lx/0x%lx redirect=0x%lx/0x%lx\n",
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT__completeValid_0,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT__completeValid_1,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT__completeIdx_0,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT__completeException_0,
|
||||
(unsigned)core->rootp->Core__DOT__backend__DOT__completeException_1,
|
||||
(uint64_t)core->rootp->Core__DOT__backend__DOT__completeCause_0,
|
||||
(uint64_t)core->rootp->Core__DOT__backend__DOT__completeCause_1,
|
||||
(uint64_t)core->rootp->Core__DOT__backend__DOT__completeRedirectPc_0,
|
||||
(uint64_t)core->rootp->Core__DOT__backend__DOT__completeRedirectPc_1);
|
||||
exit_code = 2;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user