79 lines
1.8 KiB
Makefile
79 lines
1.8 KiB
Makefile
VERILATOR = verilator
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JOBS ?= 8
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TRACE ?= 0
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FAST ?= 1
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SPLIT ?= 20000
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SPLIT_CFUNCS ?= 20000
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VERILATE_JOBS ?= $(JOBS)
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BUILD_JOBS ?= $(JOBS)
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VERILATOR_FLAGS = --cc --exe --build --verilate-jobs $(VERILATE_JOBS) --build-jobs $(BUILD_JOBS) -Wall -Wno-fatal
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VERILATOR_FLAGS += --output-split $(SPLIT) --output-split-cfuncs $(SPLIT_CFUNCS)
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ifeq ($(TRACE),1)
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VERILATOR_FLAGS += --trace
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endif
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ifeq ($(FAST),1)
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VERILATOR_FLAGS += -CFLAGS "-std=c++14 -O0"
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else
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VERILATOR_FLAGS += -CFLAGS "-std=c++14 -O2"
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endif
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SBT = env SBT_OPTS="-Dsbt.boot.directory=/tmp/sbt-boot -Dsbt.ivy.home=/tmp/sbt-ivy" COURSIER_CACHE=/tmp/coursier-cache sbt
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CHISEL_DIR = ../..
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OOO ?= 1
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ifeq ($(OOO),1)
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RUN_MAIN = CoreOoO
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GENERATED_DIR = $(CHISEL_DIR)/generated-ooo
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else
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RUN_MAIN = Core
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GENERATED_DIR = $(CHISEL_DIR)/generated
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endif
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SRC_FILES = testbench.cpp memory.cpp
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VERILOG_FILES = $(GENERATED_DIR)/Core.sv
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VERILOG_STAMP = $(GENERATED_DIR)/.Core.sv.stamp
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SCALA_SOURCES = $(shell find $(CHISEL_DIR)/src/main/scala -name '*.scala')
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TARGET = obj_dir/VCore
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.PHONY: all verilog compile run clean regenerate
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all: compile
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verilog: $(VERILOG_STAMP)
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$(VERILOG_STAMP): $(SCALA_SOURCES) $(CHISEL_DIR)/build.sbt
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@echo "Generating Verilog from Chisel..."
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cd $(CHISEL_DIR) && $(SBT) "runMain $(RUN_MAIN)"
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@touch $@
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$(VERILOG_FILES): $(VERILOG_STAMP)
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@test -f $@
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compile: $(VERILOG_FILES)
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@echo "Compiling with Verilator..."
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$(VERILATOR) $(VERILATOR_FLAGS) \
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-I$(GENERATED_DIR) \
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--top-module Core \
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-o VCore \
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$(VERILOG_FILES) $(SRC_FILES)
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run: compile
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@if [ -z "$(TEST)" ]; then \
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echo "Usage: make run TEST=<path/to/test>"; \
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exit 1; \
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fi
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./$(TARGET) $(TEST)
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test-simple: compile
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@echo "Running simple test..."
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./$(TARGET) ../../riscv-tests/isa/rv64ui-p-simple
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regenerate:
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rm -f $(VERILOG_STAMP)
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$(MAKE) verilog OOO=$(OOO)
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clean:
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rm -rf obj_dir
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rm -rf $(GENERATED_DIR)
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