fix: pass remaining riscv isa tests

src/main/scala/rename/ROB.scala

@@ -21,6 +21,7 @@ class RobEntry(p: CoreParams = CoreParams()) extends Bundle {
   val csrCmd = UInt(3.W)
   val csrRs1 = UInt(p.xlen.W)
   val csrZimm = UInt(5.W)
+  val fenceI = Bool()
 }
 
 class ROB(p: CoreParams = CoreParams()) extends Module {

src/main/scala/rename/RenameStage.scala

@@ -95,6 +95,7 @@ class RenameStage(p: CoreParams = CoreParams()) extends Module {
     e.opClass := io.in(i).opClass
     e.dest := Mux(io.in(i).writesRd, freeList.io.allocPhys(i), table.io.oldPrd(i))
     e.oldDest := table.io.oldPrd(i)
+    e.fenceI := io.in(i).isFenceI
     rob.io.allocateEntry(i) := e
   }
   rob.io.completeValid := io.completeValid
@@ -122,14 +123,18 @@ class RenameStage(p: CoreParams = CoreParams()) extends Module {
     val src2FromOlder = (0 until i).map(j =>
       io.outValid(j) && io.in(j).writesRd && io.in(j).rd =/= 0.U && io.in(j).rd === io.in(i).rs2
     ).foldLeft(false.B)(_ || _)
+    val prs1Wake = VecInit((0 until p.issueWidth).map(w => io.wbValid(w) && io.wbPhys(w) === table.io.prs1(i))).asUInt.orR
+    val prs2Wake = VecInit((0 until p.issueWidth).map(w => io.wbValid(w) && io.wbPhys(w) === table.io.prs2(i))).asUInt.orR
+    val prs1Ready = readyReg(table.io.prs1(i)) || prs1Wake
+    val prs2Ready = readyReg(table.io.prs2(i)) || prs2Wake
 
     io.outValid(i) := io.inValid(i) && canRename
     io.out(i).valid := io.outValid(i)
     io.out(i).decoded := io.in(i)
     io.out(i).prs1 := table.io.prs1(i)
     io.out(i).prs2 := table.io.prs2(i)
-    io.out(i).src1Ready := io.in(i).rs1 === 0.U || (!src1FromOlder && readyReg(table.io.prs1(i)))
-    io.out(i).src2Ready := io.in(i).rs2 === 0.U || (!src2FromOlder && readyReg(table.io.prs2(i)))
+    io.out(i).src1Ready := io.in(i).rs1 === 0.U || (!src1FromOlder && prs1Ready)
+    io.out(i).src2Ready := io.in(i).rs2 === 0.U || (!src2FromOlder && prs2Ready)
     io.out(i).prd := Mux(io.in(i).writesRd, freeList.io.allocPhys(i), table.io.oldPrd(i))
     io.out(i).oldPrd := table.io.oldPrd(i)
     io.out(i).robIdx := rob.io.allocateIdx(i)

src/main/scala/rename/RenameTable.scala

@@ -22,7 +22,14 @@ class RenameTable(p: CoreParams = CoreParams()) extends Module {
   val init = VecInit((0 until p.archRegs).map(_.U(physBits.W)))
   val speculative = RegInit(init)
   val committed = RegInit(init)
-  io.committedPhys := committed
+
+  val committedNext = WireDefault(committed)
+  for (i <- 0 until p.issueWidth) {
+    when(io.commitWen(i) && io.commitRd(i) =/= 0.U) {
+      committedNext(io.commitRd(i)) := io.commitPhys(i)
+    }
+  }
+  io.committedPhys := committedNext
 
   io.prs1(0) := speculative(io.rs1(0))
   io.prs2(0) := speculative(io.rs2(0))
@@ -33,16 +40,14 @@ class RenameTable(p: CoreParams = CoreParams()) extends Module {
   io.prs2(1) := Mux(slot0Writes && io.rd(0) === io.rs2(1), io.newPhys(0), speculative(io.rs2(1)))
   io.oldPrd(1) := Mux(slot0Writes && io.rd(0) === io.rd(1), io.newPhys(0), speculative(io.rd(1)))
 
+  committed := committedNext
   when(io.recover) {
-    speculative := committed
+    speculative := committedNext
   }.otherwise {
     for (i <- 0 until p.issueWidth) {
       when(io.wen(i) && io.rd(i) =/= 0.U) {
         speculative(io.rd(i)) := io.newPhys(i)
       }
-      when(io.commitWen(i) && io.commitRd(i) =/= 0.U) {
-        committed(io.commitRd(i)) := io.commitPhys(i)
-      }
     }
   }
 }